The GIC is logically partitioned into 2 blocks, the Distributor block
and CPU interface block. The Distributor block interfaces with the interrupt
sources, prioritizes interrupts and distributes them to the CPU interface
block. The CPU interface block connects to the processors in the system
and is responsible for priority masking and preemption handling for
the processor it is connected to.
The GIC can implement up to 8 CPU interfaces with each CPU interface
being able to see up to 1020 interrupts. The GIC assigns interrupt ID
numbers 0-1019 as follows:
- Interrupt numbers 0-31 are used for interrupts private to a
CPU interface. These private interrupts are banked in the Distributor.
- Banked interrupt number 0-15 are used for Software Generated Interrupts
or SGIs.
- Banked interrupt number 16-31 are used for Private Peripheral Interrupts
or PPIs.
- Interrupt numbers 32-1019 are used for Shared Peripheral Interrupts
or SPIs.
- Interrupt numbers 1020-1023 are reserved.
In the SoC Technical Reference Manual, the MPU IRQs 0 to N map to
GIC interrupt numbers 32 to (N+32) where (N+1) is the total number of
Shared Peripheral Interrupts implemented.
For instance on OMAP5430, MPU IRQ 0 to 159 maps to GIC interrupt number
32 to 191.
This module is written for GIC v2.0, however it is backwards compatible
with GIC v1.0
GIC allows configuring an interrupt as a Group 0 or a Group 1 interrupt.
Group 0 interrupts are Secure interrupts and Group 1 interrupts are
Non-secure interrupts.
In general GIC supports priority values 0 thru 255.
In GIC, interrupts with lower priority numbers have higher priority.
On Keystone2 devices, this module supports zero-latency interrupts. A
zero-latency interrupt does not go through the SYS/BIOS dispatcher and
thus has a faster response time. Since zero-latency interrupts bypass the
dispatcher, their handler function cannot call any SYS/BIOS APIs.
This module implements zero-latency interrupts by forwarding the interrupt
to the target CPU using FIQ signal. Therefore, in order to configure an
interrupt as a zero-latency interrupt, the Hwi type needs to be changed
to FIQ when creating or constructing a Hwi.
const Hwi_NUM_INTERRUPTS |
|
Number of interrupts implemented in GIC
#define Hwi_NUM_INTERRUPTS (UInt)992
enum Hwi_ExcType |
|
typedef enum Hwi_ExcType {
Hwi_ExcType_Synchronous,
Hwi_ExcType_SError
} Hwi_ExcType;
enum Hwi_MaskingOption |
|
Shorthand interrupt masking options
typedef enum Hwi_MaskingOption {
Hwi_MaskingOption_NONE,
Hwi_MaskingOption_ALL,
Hwi_MaskingOption_SELF,
Hwi_MaskingOption_BITMASK,
Hwi_MaskingOption_LOWER
} Hwi_MaskingOption;
VALUES
MaskingOption_NONE
No interrupts are disabled
MaskingOption_ALL
All interrupts are disabled
MaskingOption_SELF
Only this interrupt is disabled
MaskingOption_BITMASK
User supplies interrupt enable masks
MaskingOption_LOWER
All current and lower priority
interrupts are disabled.
Only a few targets/devices truly
support this masking option. For those
that don't, this setting is treated
the same as MaskingOption_SELF.
enum Hwi_RoutingMode |
|
Routing mode. ANY or NODE
typedef enum Hwi_RoutingMode {
Hwi_RoutingMode_NODE,
// Route interrupt to node specified by
affinity fields
Hwi_RoutingMode_ALL
// Route interrupt to all nodes
} Hwi_RoutingMode;
enum Hwi_Type |
|
Interrupt type. IRQ or FIQ
typedef enum Hwi_Type {
Hwi_Type_IRQ,
// IRQ interrupt
Hwi_Type_FIQ
// FIQ interrupt
} Hwi_Type;
typedef Hwi_ExceptionHookFuncPtr |
|
Exception hook function type definition
typedef Hwi_FuncPtr |
|
Hwi create function type definition
typedef Void (*Hwi_FuncPtr)(UArg);
typedef Hwi_Irp |
|
Interrupt Return Pointer
DETAILS
This is the address of the interrupted instruction.
struct Hwi_ExcContext |
|
Exception Context - Register contents at the time of an exception
typedef struct Hwi_ExcContext {
Ptr threadHandle;
Ptr threadStack;
SizeT threadStackSize;
Ptr x0;
Ptr x1;
Ptr x2;
Ptr x3;
Ptr x4;
Ptr x5;
Ptr x6;
Ptr x7;
Ptr x8;
Ptr x9;
Ptr x10;
Ptr x11;
Ptr x12;
Ptr x13;
Ptr x14;
Ptr x15;
Ptr x16;
Ptr x17;
Ptr x18;
Ptr x19;
Ptr x20;
Ptr x21;
Ptr x22;
Ptr x23;
Ptr x24;
Ptr x25;
Ptr x26;
Ptr x27;
Ptr x28;
Ptr x29;
Ptr x30;
Ptr sp;
Ptr elr;
Ptr spsr;
Ptr esr;
} Hwi_ExcContext;
struct Hwi_Gicc |
|
Generic Interrupt Controller CPU Interface. Symbol "Hwi_gicc" is
a physical device
typedef struct Hwi_Gicc {
UInt32 CTLR;
// 0x0000 CPU Interface Control Register
UInt32 PMR;
// 0x0004 Interrupt Priority Mask Register
UInt32 BPR;
// 0x0008 Binary Point Register
UInt32 IAR;
// 0x000C Interrupt Acknowledge Register
UInt32 EOIR;
// 0x0010 End Of Interrupt Register
UInt32 RPR;
// 0x0014 Running Priority Register
UInt32 HPPIR;
// 0x0018 Highest Priority Pending Interrupt
Register
UInt32 ABPR;
// 0x001C Aliased Binary Point Register
UInt32 AIAR;
// 0x0020 Aliased IAR Register
UInt32 AEOIR;
// 0x0024 Aliased EOI Register
UInt32 AHPPIR;
// 0x0028 Aliased HPPI Register
UInt32 hole0[41];
// 0x002C-0x00CC
UInt32 APR0;
// 0x00D0 Active Priority Register
UInt32 hole1[3];
// 0x00D4-0x00DC
UInt32 NSAPR0;
// 0x00E0 Non-secure Active Priority Register
UInt32 hole2[6];
// 0x00E4-0x00F8
UInt32 IIDR;
// 0x00FC CPU Interface Id Register
UInt32 hole3[960];
// 0x0100-0x0FFC
UInt32 DIR;
// 0x1000 Deactivate Interrupt Register
} Hwi_Gicc;
struct Hwi_Gicd |
|
Generic Interrupt Controller Distributor. Symbol "Hwi_gicd" is
a physical device
typedef struct Hwi_Gicd {
UInt32 CTLR;
// 0x0000 Distributor Control Register
UInt32 TYPER;
// 0x0004 Interrupt Controller Type Register
UInt32 IIDR;
// 0x0008 Distributor Implementor Id Register
UInt32 hole0[13];
// 0x000C-0x03C
UInt32 SETSPI_NSR;
// 0x0040 Set SPI Register
UInt32 hole1;
// 0x0044
UInt32 CLRSPI_NSR;
// 0x0048 Clear SPI Register
UInt32 hole2;
// 0x004C
UInt32 SETSPI_SR;
// 0x0050 Set SPI Register
UInt32 hole3;
// 0x0054
UInt32 CLRSPI_SR;
// 0x0058 Clear SPI Register
UInt32 hole4[9];
// 0x005C-0x007C
UInt32 IGROUPR[32];
// 0x0080 Interrupt Group Registers
UInt32 ISENABLER[32];
// 0x0100 Interrupt Set-Enable Registers
UInt32 ICENABLER[32];
// 0x0180 Interrupt Clear-Enable Registers
UInt32 ISPENDR[32];
// 0x0200 Interrupt Set-Pending Registers
UInt32 ICPENDR[32];
// 0x0280 Interrupt Clear-Pending Registers
UInt32 ISACTIVER[32];
// 0x0300 Interrupt Set-Active Registers
UInt32 ICACTIVER[32];
// 0x0380 Interrupt Clear-Active Registers
UInt8 IPRIORITYR[992];
// 0x0400 Interrupt Priority Registers
UInt32 hole5[8];
// 0x07E0-0x07FC
UInt32 ITARGETSR[8];
// 0x0800 Interrupt Processor Targets
Register
UInt32 hole6[248];
// 0x0820-0x0BFC
UInt32 ICFGR[64];
// 0x0C00 Interrupt Configuration Registers
UInt32 IGRPMODR[32];
// 0x0D00 Interrupt Group Modifier Registers
UInt32 hole7[32];
// 0x0D80-0x0DFC
UInt32 NSACR[64];
// 0x0E00 NonSecure Access Control Registers
UInt32 SGIR;
// 0x0F00 Software Generated Interrupt
Register
UInt32 hole8[3];
// 0x0F04-0x0F0C
UInt32 CPENDSGIR[4];
// 0x0F10 SGI Clear-Pending Registers
UInt32 SPENDSGIR[4];
// 0x0F20 SGI Set-Pending Registers
UInt32 hole9[5172];
// 0x0F30-0x5FFC
UInt64 IROUTER[992];
// 0x6000 Interrupt Routing Registers
UInt32 hole10[4160];
// 0x7F00-0xBFFC
UInt32 ESTATUSR;
// 0xC000 Extended Status Register
UInt32 ERRTESTR;
// 0xC004 Error Test Register
UInt32 hole11[31];
// 0xC008-0xC080
UInt32 SPISR[30];
// 0xC084 SPI Status Registers
UInt32 hole12[4021];
// 0xC0FC-0xFFCC
UInt32 PIDR4;
// 0xFFD0 Peripheral ID4 Register
UInt32 PIDR5;
// 0xFFD4 Peripheral ID5 Register
UInt32 PIDR6;
// 0xFFD8 Peripheral ID6 Register
UInt32 PIDR7;
// 0xFFDC Peripheral ID7 Register
UInt32 PIDR0;
// 0xFFE0 Peripheral ID0 Register
UInt32 PIDR1;
// 0xFFE4 Peripheral ID1 Register
UInt32 PIDR2;
// 0xFFE8 Peripheral ID2 Register
UInt32 PIDR3;
// 0xFFEC Peripheral ID3 Register
UInt32 CIDR0;
// 0xFFF0 Component ID0 Register
UInt32 CIDR1;
// 0xFFF4 Component ID1 Register
UInt32 CIDR2;
// 0xFFF8 Component ID2 Register
UInt32 CIDR3;
// 0xFFFC Component ID3 Register
} Hwi_Gicd;
struct Hwi_Gicr |
|
Generic Interrupt Controller Redistributor Interface (RD_base).
Symbol "Hwi_gicr" is a physical device
typedef struct Hwi_Gicr {
UInt32 CTLR;
// 0x0000 Redistributor Control Register
UInt32 IIDR;
// 0x0004 Implementor Id Register
UInt32 TYPER[2];
// 0x0008 Redistributor Type Register
UInt32 hole0;
// 0x0010
UInt32 WAKER;
// 0x0014 Power Management Control Register
UInt32 hole1[22];
// 0x0018-0x006C
UInt32 PROPBASER[2];
// 0x0070 LPI Config Table Base Register
UInt32 PENDBASER[2];
// 0x0078 LPI Pending Table Base Register
} Hwi_Gicr;
struct Hwi_Gics |
|
Generic Interrupt Controller Redistributor Interface (SGI_base).
Symbol "Hwi_gics" is a physical device
typedef struct Hwi_Gics {
UInt32 hole0[32];
// 0x0000-0x007C
UInt32 IGROUPR0;
// 0x0080 Interrupt Group Register
UInt32 hole1[31];
// 0x0084-0x00FC
UInt32 ISENABLER0;
// 0x0100 Interrupt Set-Enable Register
UInt32 hole2[31];
// 0x0104-0x017C
UInt32 ICENABLER0;
// 0x0180 Interrupt Set-Enable Register
UInt32 hole3[31];
// 0x0184-0x01FC
UInt32 ISPENDR0;
// 0x0200 Interrupt Set-Enable Register
UInt32 hole4[31];
// 0x0204-0x027C
UInt32 ICPENDR0;
// 0x0280 Interrupt Set-Enable Register
UInt32 hole5[31];
// 0x0284-0x02FC
UInt32 ISACTIVER0;
// 0x0300 Interrupt Set-Enable Register
UInt32 hole6[31];
// 0x0304-0x037C
UInt32 ICACTIVER0;
// 0x0380 Interrupt Set-Enable Register
UInt32 hole7[31];
// 0x0384-0x03FC
UInt8 IPRIORITYR[32];
// 0x0400 Interrupt Priority Registers
UInt32 hole8[504];
// 0x0420-0x0BFC
UInt32 ICFGR[2];
// 0x0C00 Interrupt Configuration Registers
UInt32 hole9[62];
// 0x0C08-0x0CFC
UInt32 IGRPMODR0;
// 0x0D00 Interrupt Group Modifier Register
UInt32 hole10[63];
// 0x0D04-0x0DFC
UInt32 NSACR;
// 0x0E00 NonSecure Access Control Register
} Hwi_Gics;
struct Hwi_HookSet |
|
Hwi hook set type definition
typedef struct Hwi_HookSet {
Void (*registerFxn)(Int);
} Hwi_HookSet;
DETAILS
The functions that make up a hookSet have certain restrictions. They
cannot call any Hwi instance functions other than Hwi_getHookContext()
and Hwi_setHookContext(). For all practical purposes, they should treat
the Hwi_Handle passed to these functions as an opaque handle.
struct Hwi_IntAffinity |
|
Interrupt affinity type. Stores the hierarchical address (composed
of different affinity levels) that uniquely identifies the core or
processing element (PE) an interrupt is routed to
typedef struct Hwi_IntAffinity {
UInt8 aff0;
// Affinity level 0 - CoreId within cluster
UInt8 aff1;
// Affinity level 1 - Cluster Id
// Routing Mode - ALL or particular NODE
} Hwi_IntAffinity;
DETAILS
The routingMode field determines whether an interrupt is routed to
all nodes or a node identified by the affinity fields. This field
takes the value Hwi_RoutingMode_ANY and Hwi_RoutingMode_NODE.
If
BIOS.smpEnabled is true then,
all interrupts are forwarded to core 0 by default.
If
BIOS.smpEnabled is false then,
all interrupts are forwarded to all participating nodes.
CONSTRAINTS
This config param is ignored if
Core.bootMaster is
set to false.
struct Hwi_SgiIntAffinity |
|
Sgi interrupt affinity type. Stores affinity and routing mode
information that is used to determine which cores will the generated
SGI be routed to
typedef struct Hwi_SgiIntAffinity {
UInt8 targetList;
// Bit map of target cores
UInt8 aff1;
// Identifies the target cluster
// Routing Mode - ALL or NODE target list
} Hwi_SgiIntAffinity;
DETAILS
The routingMode field determines whether a generated SGI is routed to
all cores except the core generating the SGI (Hwi_RoutingMode_ALL) or
to list of target cores identified by the "targetList" and "aff1"
fields (Hwi_RoutingMode_NODE).
struct Hwi_StackInfo |
|
Structure contains Hwi stack usage info
typedef struct Hwi_StackInfo {
SizeT hwiStackPeak;
SizeT hwiStackSize;
Ptr hwiStackBase;
} Hwi_StackInfo;
DETAILS
Used by getStackInfo() and viewGetStackInfo() functions
config Hwi_A_badSGIIntNum // module-wide |
|
Assert raised when an interrupt number >= 16 is
passed to Hwi_raiseSGI() function
config Hwi_BPR // module-wide |
|
GIC Binary Point Register value
extern const UInt Hwi_BPR;
DETAILS
Defines the point at which the priority value fields split into
two parts, the group priority field and the sub-priority field.
When running in SECURE mode, BPR applies to Group 0 interrupts
and when running in NON-SECURE mode, BPR applies to Group 1
interrupts.
The group priority field determines interrupt preemption in case
of nested interrupts whereas sub-priority field is used to determine
priority within a group when multiple interrrupts belonging to the
same group are pending.
Valid BPR values are from 0-7 with the minimum value supported being
implementation defined and in the range 0-3.
-------------------------------------------------------
| BPR value | Group priority field | Sub-priority field |
-------------------------------------------------------
| 0 | [7:1] | [0] |
| 1 | [7:2] | [1:0] |
| 2 | [7:3] | [2:0] |
| 3 | [7:4] | [3:0] |
| 4 | [7:5] | [4:0] |
| 5 | [7:6] | [5:0] |
| 6 | [7] | [6:0] |
| 7 | No preemption | [7:0] |
-------------------------------------------------------
config Hwi_DEFAULT_INT_PRIORITY // module-wide |
|
Default Interrupt Priority
extern const UInt Hwi_DEFAULT_INT_PRIORITY;
DETAILS
Set to one level higher than minimum supported priority.
config Hwi_E_alreadyDefined // module-wide |
|
Error raised when an attempt is made to create a Hwi
that has already been created
extern const Error_Id Hwi_E_alreadyDefined;
config Hwi_E_badIntNum // module-wide |
|
Error raised if an attempt is made to create a Hwi
with an interrupt number greater than Hwi_NUM_INTERRUPTS - 1
config Hwi_E_exception // module-wide |
|
Error raised when an exception occurs
config Hwi_E_handleNotFound // module-wide |
|
Error raised when Hwi handle referenced in Hwi_delete()
is not found in the Hwi dispatch table
extern const Error_Id Hwi_E_handleNotFound;
config Hwi_E_undefined // module-wide |
|
Error raised when an undefined interrupt has fired
config Hwi_LD_end // module-wide |
|
Issued just after return from Hwi function (with interrupts disabled)
config Hwi_LM_begin // module-wide |
|
Issued just prior to Hwi function invocation (with interrupts disabled)
config Hwi_MIN_INT_PRIORITY // module-wide |
|
Minimum Interrupt Priority
extern const UInt Hwi_MIN_INT_PRIORITY;
config Hwi_NUM_PRIORITY_BITS // module-wide |
|
Number of Priority bits implemented
extern const UInt Hwi_NUM_PRIORITY_BITS;
DETAILS
On OMAP543x running in non-secure mode, only most significant 4
priority bits are available for use. The least significant 4 bits
are always 0.
config Hwi_dispatcherAutoNestingSupport // module-wide |
|
Include interrupt nesting logic in interrupt dispatcher?
extern const Bool Hwi_dispatcherAutoNestingSupport;
DETAILS
Default is true.
This option provides the user with the ability to optimize
interrupt dispatcher performance when support for interrupt
nesting is not required.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that manipulates interrupt mask
registers and enables and disables interrupts before and
after invoking the user's Hwi function.
Set this parameter to false if you don't need interrupts
enabled during the execution of your Hwi functions.
config Hwi_dispatcherIrpTrackingSupport // module-wide |
|
Controls whether the
dispatcher retains the interrupted thread's return address
extern const Bool Hwi_dispatcherIrpTrackingSupport;
DETAILS
This option is enabled by default.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that keeps track of the interrupt's
return address and provide a small savings in interrupt latency.
The application can get an interrupt's most recent return
address using the
getIrp API.
config Hwi_dispatcherSwiSupport // module-wide |
|
Include Swi scheduling logic in interrupt dispatcher?
extern const Bool Hwi_dispatcherSwiSupport;
DETAILS
Default is inherited from
BIOS.swiEnabled, which is true by default.
This option provides the user with the ability to optimize
interrupt dispatcher performance when it is known that Swis
will not be posted from any of their Hwi threads.
WARNING
Setting this parameter to false will disable the logic in
the interrupt dispatcher that invokes the Swi scheduler
prior to returning from an interrupt.
With this setting, Swis MUST NOT be posted from Hwi functions!
config Hwi_dispatcherTaskSupport // module-wide |
|
Include Task scheduling logic in interrupt dispatcher?
extern const Bool Hwi_dispatcherTaskSupport;
DETAILS
Default is inherited from
BIOS.taskEnabled, which is true by default.
This option provides the user with the ability to optimize
interrupt dispatcher performance when it is known that no
Task scheduling APIs (ie
Semaphore_post()) will be executed from any of their Hwi threads.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that invokes the Task scheduler
prior to returning from an interrupt.
config Hwi_enableDecode // module-wide |
|
Enable full exception decoding, default is true
extern const Bool Hwi_enableDecode;
DETAILS
When enabled, the exception handler will fully
decode an exception and dump the registers to the
system console.
When set to false, only an Error is printed on the console.
In either case, the full exception context is always
saved and visible with ROV.
config Hwi_enableSecureMode // module-wide |
|
Security Mode
extern const Bool Hwi_enableSecureMode;
DETAILS
This field specifies the MPU's security mode. The MPU's security mode
determines the type of accesses to the GIC i.e. if the MPU is in secure
mode, all accesses to the GIC are secure and if the MPU is in non-secure
mode, all accesses to the GIC are non-secure.
An exception to the above rule can be seen on certain devices like
Keystone 2, where all GIC acceses are secure irrespective of the MPU's
security state.
enableSecureMode should be set to true for such
devices.
config Hwi_sErrorExcHookFunc // module-wide |
|
User SError Exception hook function
DETAILS
Called just after the exception context has been initialized.
This function will be run on the ISR stack.
This function must run to completion.
It is called without any Task or Swi scheduling protection
and therefore can not call any functions that may cause a Swi or Task
scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
config Hwi_syncExcHookFunc // module-wide |
|
User Synchronous Exception hook function
DETAILS
Called just after the exception context has been initialized.
This function will be run on the ISR stack.
This function must run to completion.
It is called without any Task or Swi scheduling protection
and therefore can not call any functions that may cause a Swi or Task
scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
extern Hwi_gicd |
|
Hwi_Gicd Hwi_gicd; // linked as extern ti_sysbios_family_arm_gicv3_Hwi_gicd
Hwi_clearInterrupt() // module-wide |
|
Clear a specific interrupt
Void Hwi_clearInterrupt(UInt intNum);
ARGUMENTS
intNum
interrupt number to clear
DETAILS
Clears a specific interrupt's pending status.
The implementation is family-specific.
Hwi_disable() // module-wide |
|
Globally disable interrupts
macro UInt Hwi_disable();
RETURNS
opaque key for use by Hwi_restore()
DETAILS
Hwi_disable globally disables hardware interrupts and returns an
opaque key indicating whether interrupts were globally enabled or
disabled on entry to Hwi_disable().
The actual value of the key is target/device specific and is meant
to be passed to Hwi_restore().
Call Hwi_disable before a portion of a function that needs
to run without interruption. When critical processing is complete, call
Hwi_restore or Hwi_enable to reenable hardware interrupts.
Servicing of interrupts that occur while interrupts are disabled is
postponed until interrupts are reenabled. However, if the same type
of interrupt occurs several times while interrupts are disabled,
the interrupt's function is executed only once when interrupts are
reenabled.
A context switch can occur when calling Hwi_enable or Hwi_restore if
an enabled interrupt occurred while interrupts are disabled.
Hwi_disable may be called from main(). However, since Hwi interrupts
are already disabled in main(), such a call has no effect.
NOTE
Disables only IRQ interrupts
CONSTRAINTS
If a Task switching API such as
Semaphore_pend(),
Semaphore_post(),
Task_sleep(), or
Task_yield()
is invoked which results in a context switch while
interrupts are disabled, an embedded call to
Hwi_enable occurs
on the way to the new thread context which unconditionally re-enables
interrupts. Interrupts will remain enabled until a subsequent
Hwi_disable
invocation.
Swis always run with interrupts enabled.
See
Swi_post() for a discussion Swis and
interrupts.
Hwi_disableIRQ() // module-wide |
|
Disable IRQ interrupts
macro UInt Hwi_disableIRQ();
RETURNS
previous IRQ interrupt enable/disable state
NOTE
Same as Hwi_disable()
Hwi_disableInterrupt() // module-wide |
|
Disable a specific interrupt
UInt Hwi_disableInterrupt(UInt intNum);
ARGUMENTS
intNum
interrupt number to disable
RETURNS
key to restore previous enable/disable state
DETAILS
Disable a specific interrupt identified by an interrupt number.
Hwi_enable() // module-wide |
|
Globally enable interrupts
RETURNS
opaque key for use by Hwi_restore()
DETAILS
Hwi_enable globally enables hardware interrupts and returns an
opaque key indicating whether interrupts were globally enabled or
disabled on entry to Hwi_enable().
The actual value of the key is target/device specific and is meant
to be passed to Hwi_restore().
This function is
called as part of SYS/BIOS Startup_POST_APP_MAIN phase.
Hardware interrupts are enabled unless a call to Hwi_disable disables
them.
Servicing of interrupts that occur while interrupts are disabled is
postponed until interrupts are reenabled. However, if the same type
of interrupt occurs several times while interrupts are disabled,
the interrupt's function is executed only once when interrupts are
reenabled.
A context switch can occur when calling Hwi_enable or Hwi_restore if
an enabled interrupt occurred while interrupts are disabled.
Any call to Hwi_enable enables interrupts, even if Hwi_disable has
been called several times.
Hwi_enable must not be called from main().
NOTE
Enables only IRQ interrupts
Hwi_enableIRQ() // module-wide |
|
Enable IRQ interrupts
macro UInt Hwi_enableIRQ();
RETURNS
previous IRQ interrupt enable/disable state
NOTE
Same as Hwi_enable()
Hwi_enableInterrupt() // module-wide |
|
Enable a specific interrupt
UInt Hwi_enableInterrupt(UInt intNum);
ARGUMENTS
intNum
interrupt number to enable
RETURNS
key to restore previous enable/disable state
DETAILS
Enables a specific interrupt identified by an interrupt number.
Hwi_getCoreStackInfo() // module-wide |
|
Get Hwi stack usage Info for the specified coreId
Bool Hwi_getCoreStackInfo(
IHwi_StackInfo *
stkInfo,
Bool computeStackDepth,
UInt coreId);
ARGUMENTS
stkInfo
pointer to structure of type StackInfo
computeStackDepth
decides whether to compute stack depth
coreId
core whose stack info needs to be retrieved
RETURNS
boolean to indicate a stack overflow
DETAILS
getCoreStackInfo returns the Hwi stack usage info for the specified
coreId to its calling function by filling stack base address,
stack size and stack peak fields in the
StackInfo structure.
This function should be used only in applications built with
ti.sysbios.BIOS.smpEnabled set to true.
getCoreStackInfo accepts three arguments, a pointer to a structure
of type
StackInfo, a boolean and a coreId. If the boolean
is set to true, the function computes the stack depth and fills the
stack peak field in the StackInfo structure. If a stack overflow
is detected, the stack depth is not computed. If the boolean is
set to false, the function only checks for a stack overflow.
The isr stack is always checked for an overflow and a boolean
is returned to indicate whether an overflow occured.
Below is an example of calling getCoreStackInfo() API:
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/hal/Hwi.h>
#include <ti/sysbios/hal/Core.h>
#include <ti/sysbios/knl/Task.h>
...
Void idleTask()
{
UInt idx;
Hwi_StackInfo stkInfo;
Bool stackOverflow = FALSE;
// Request stack depth for each core's Hwi stack and check for
// overflow
for (idx = 0; idx < Core_numCores; idx++) {
stackOverflow = Hwi_getCoreStackInfo(&stkInfo, TRUE, idx);
// Alternately, we can omit the request for stack depth and
// request only the stack base and stack size (the check for
// stack overflow is always performed):
//
// stackOverflow = Hwi_getCoreStackInfo(&stkInfo, FALSE, idx);
if (stackOverflow) {
// isr Stack Overflow detected
}
}
}
Int main(Int argc, char* argv[])
{
...
BIOS_start();
return (0);
}
Hwi_getHandle() // module-wide |
|
Returns Hwi_Handle associated with intNum
ARGUMENTS
intNum
interrupt number
Hwi_getStackInfo() // module-wide |
|
Get Hwi stack usage Info
Bool Hwi_getStackInfo(
IHwi_StackInfo *
stkInfo,
Bool computeStackDepth);
ARGUMENTS
stkInfo
pointer to structure of type StackInfo
computeStackDepth
decides whether to compute stack depth
RETURNS
boolean to indicate a stack overflow
DETAILS
getStackInfo returns the Hwi stack usage info to its calling
function by filling stack base address, stack size and stack
peak fields in the
StackInfo structure.
getStackInfo accepts two arguments, a pointer to a structure
of type
StackInfo and a boolean. If the boolean is set
to true, the function computes the stack depth and fills the
stack peak field in the StackInfo structure. If a stack overflow
is detected, the stack depth is not computed. If the boolean is
set to false, the function only checks for a stack overflow.
The isr stack is always checked for an overflow and a boolean
is returned to indicate whether an overflow occured.
Below is an example of calling getStackInfo() API:
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/hal/Hwi.h>
#include <ti/sysbios/knl/Swi.h>
#include <ti/sysbios/knl/Task.h>
Swi_Handle swi0;
volatile Bool swiStackOverflow = FALSE;
Void swi0Fxn(UArg arg1, UArg arg2)
{
Hwi_StackInfo stkInfo;
// Request stack depth
swiStackOverflow = Hwi_getStackInfo(&stkInfo, TRUE);
// Alternately, we can omit the request for stack depth and
// request only the stack base and stack size (the check for
// stack overflow is always performed):
//
// swiStackOverflow = Hwi_getStackInfo(&stkInfo, FALSE);
if (swiStackOverflow) {
// isr Stack Overflow detected
}
}
Void idleTask()
{
Swi_post(swi0);
}
Int main(Int argc, char* argv[])
{
swi0 = Swi_create(swi0Fxn, NULL, NULL);
BIOS_start();
return (0);
}
Hwi_post() // module-wide |
|
Generate an interrupt for test purposes
Void Hwi_post(UInt intNum);
ARGUMENTS
intNum
ID of interrupt to generate
Hwi_restore() // module-wide |
|
Globally restore interrupts
macro Void Hwi_restore(UInt key);
ARGUMENTS
key
enable/disable state to restore
DETAILS
Hwi_restore globally restores interrupts to the state determined
by the key argument provided by a previous invocation of Hwi_disable.
A context switch may occur when calling Hwi_restore if Hwi_restore
reenables interrupts and another Hwi occurred while interrupts were
disabled.
Hwi_restore may be called from main(). However, since Hwi_enable
cannot be called from main(), interrupts are always disabled in
main(), and a call to Hwi_restore has no effect.
NOTE
Restores only IRQ interrupts
Hwi_restoreIRQ() // module-wide |
|
Restore IRQ interrupts
macro Void Hwi_restoreIRQ(UInt key);
ARGUMENTS
key
enable/disable state to restore
NOTE
Same as Hwi_restore()
Hwi_restoreInterrupt() // module-wide |
|
Restore a specific interrupt's enabled/disabled state
Void Hwi_restoreInterrupt(UInt intNum, UInt key);
ARGUMENTS
intNum
interrupt number to restore
key
key returned from enableInt or disableInt
DETAILS
Restores a specific interrupt identified by an interrupt number.
restoreInterrupt is generally used to restore an interrupt to its state
before
disableInterrupt or
enableInterrupt was
invoked
Hwi_setPriority() // module-wide |
|
Set an interrupt's priority
Void Hwi_setPriority(UInt intNum, UInt priority);
ARGUMENTS
intNum
ID of interrupt
priority
priority
DETAILS
Not an instance function so that it can be used
with non-dispatched interrupts.
Hwi_startup() // module-wide |
|
Initially enable interrupts
DETAILS
Called within BIOS_start
Module-Wide Built-Ins |
|
// Get this module's unique id
Bool Hwi_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Hwi_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Hwi_Module_getMask();
// Returns the diagnostics mask for this module
Void Hwi_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
Instance Object Types |
|
typedef struct Hwi_Object Hwi_Object;
// Opaque internal representation of an instance object
// Client reference to an instance object
typedef struct Hwi_Struct Hwi_Struct;
// Opaque client structure large enough to hold an instance object
// Convert this instance structure pointer into an instance handle
// Convert this instance handle into an instance structure pointer
Instance Config Parameters |
|
typedef struct Hwi_Params {
// Instance config-params structure
// Common per-instance configs
UArg arg;
// ISR function argument. Default is 0
Bool enableInt;
// Enable this interrupt when object is created? Default is true
Int eventId;
// Interrupt event ID (Interrupt Selection Number)
// The interrupt controller is designed for priority based interrupts
Int priority;
// Hwi instance interrupt priority
UInt triggerSensitivity;
// Set an interrupt's trigger sensitivity
// Interrupt type (IRQ/FIQ). Default is IRQ
} Hwi_Params;
// Initialize this config-params structure with supplier-specified defaults before instance creation
config Hwi_Params.arg // instance |
|
ISR function argument. Default is 0
config Hwi_Params.enableInt // instance |
|
Enable this interrupt when object is created? Default is true
config Hwi_Params.eventId // instance |
|
Interrupt event ID (Interrupt Selection Number)
DETAILS
Default is -1.
Not all targets/devices support this instance parameter.
On those that don't, this parameter is ignored.
config Hwi_Params.maskSetting // instance |
|
The interrupt controller is designed for priority based interrupts
config Hwi_Params.priority // instance |
|
Hwi instance interrupt priority
DETAILS
The default value of -1 is used as a flag to indicate
the lowest (logical) device-specific priority value.
Not all targets/devices support this instance parameter.
On those that don't, this parameter is ignored.
Valid priorities are device dependent and their
nesting behaviors depend on the
BPR setting.
See the ARM GIC Architecture Specification v2.0 document for more
details.
config Hwi_Params.triggerSensitivity // instance |
|
Set an interrupt's trigger sensitivity
...
UInt triggerSensitivity;
DETAILS
2-bit field that configures the trigger sensitivity of an
interrupt.
On the Cortex-A15, all software generated interrupts (SGI)
are edge-triggered (b10) and all private peripheral interrupts (PPI)
are level-sensitive (b01). The trigger sensitivity of these
interrupt types cannot be changed.
For shared peripheral interrupts (SPI), the LSB of the bit-pair
is read only and is always 1. The MSB of the bit-pair can be
altered to change trigger sensitivity.
Possible bit-pair encodings for Cortex-A15 SPIs:
b01 Interrupt is active-High level-sensitive (default)
b11 Interrupt is rising edge-sensitive
For more information please refer section 4.3.13 on
Interrupt Configuration Registers (GICD_ICFGRn) in
ARM Generic Interrupt Controller Architecure Spec v2.0
CONSTRAINTS
This Hwi param is ignored if
Core.bootMaster is
set to false.
config Hwi_Params.type // instance |
|
Interrupt type (IRQ/FIQ). Default is IRQ
NOTE
FIQs are only supported when
enableSecureMode is set to
true.
Runtime Instance Creation |
|
// Allocate and initialize a new instance object and return its handle
// Initialize a new instance object inside the provided structure
ARGUMENTS
intNum
interrupt number
hwiFxn
pointer to ISR function
params
per-instance config params, or NULL to select default values (target-domain only)
eb
active error-handling block, or NULL to select default policy (target-domain only)
DETAILS
A Hwi dispatcher table entry is created and filled with the
function specified by the fxn parameter and the attributes
specified by the params parameter.
If params is NULL, the Hwi's dispatcher properties are assigned a
default set of values. Otherwise, the following properties
are specified by a structure of type Hwi_Params.
- The arg element is a generic argument that is passed to the plugged
function as its only parameter. The default value is 0.
- The enableInt element determines whether the interrupt should be
enabled in the IER by create.
- The maskSetting element defines the dispatcherAutoNestingSupport
behavior of the interrupt.
Hwi_create returns a pointer to the created Hwi object.
Instance Deletion |
|
// Finalize and free this previously allocated instance object, setting the referenced handle to NULL
// Finalize the instance object inside the provided structure
Hwi_getFunc() // instance |
|
Get Hwi function and arg
ARGUMENTS
handle
handle of a previously-created Hwi instance object
arg
pointer for returning hwi's ISR function argument
RETURNS
hwi's ISR function
Hwi_getHookContext() // instance |
|
Get hook instance's context for a Hwi
Ptr Hwi_getHookContext(
Hwi_Handle handle,
Int id);
ARGUMENTS
handle
handle of a previously-created Hwi instance object
RETURNS
hook instance's context for hwi
Hwi_getIrp() // instance |
|
Get address of interrupted instruction
ARGUMENTS
handle
handle of a previously-created Hwi instance object
RETURNS
most current IRP of a Hwi
Hwi_reconfig() // instance |
|
Reconfigure a dispatched interrupt
ARGUMENTS
handle
handle of a previously-created Hwi instance object
Hwi_setFunc() // instance |
|
Overwrite Hwi function and arg
ARGUMENTS
handle
handle of a previously-created Hwi instance object
fxn
pointer to ISR function
arg
argument to ISR function
DETAILS
Replaces a Hwi object's hwiFxn function originally
provided in
create.
CONSTRAINTS
Hwi_setFunc() is not thread safe. This means that the new value for
for 'fxn' may be temporarily paired with the previous value for 'arg'
if pre-emption occurs within the execution of Hwi_setFunc().
To guard against this condition, surround the Hwi_setFunc() call with
calls to Hwi_disable() and Hwi_restore():
key = Hwi_disable();
Hwi_setFunc(newFunc, newArg);
Hwi_restore(key);
Hwi_setHookContext() // instance |
|
Set hook instance's context for a Hwi
Void Hwi_setHookContext(
Hwi_Handle handle,
Int id,
Ptr hookContext);
ARGUMENTS
handle
handle of a previously-created Hwi instance object
id
hook instance's ID
hookContext
value to write to context
Instance Convertors |
|
// unconditionally move one level up the inheritance hierarchy
// conditionally move one level down the inheritance hierarchy; NULL upon failure
Instance Built-Ins |
|
Int Hwi_Object_count();
// The number of statically-created instance objects
// The handle of the i-th statically-created instance object (array == NULL)
// The handle of the first dynamically-created instance object, or NULL
// The handle of the next dynamically-created instance object, or NULL
// The heap used to allocate dynamically-created instance objects
// The label associated with this instance object
// The name of this instance object
const Hwi.NUM_INTERRUPTS |
|
Number of interrupts implemented in GIC
const Hwi.NUM_INTERRUPTS = 992;
C SYNOPSIS
enum Hwi.ExcType |
|
values of type Hwi.ExcType
const Hwi.ExcType_Synchronous;
const Hwi.ExcType_SError;
C SYNOPSIS
enum Hwi.MaskingOption |
|
Shorthand interrupt masking options
values of type Hwi.MaskingOption
const Hwi.MaskingOption_NONE;
const Hwi.MaskingOption_ALL;
const Hwi.MaskingOption_SELF;
const Hwi.MaskingOption_BITMASK;
const Hwi.MaskingOption_LOWER;
VALUES
MaskingOption_NONE
No interrupts are disabled
MaskingOption_ALL
All interrupts are disabled
MaskingOption_SELF
Only this interrupt is disabled
MaskingOption_BITMASK
User supplies interrupt enable masks
MaskingOption_LOWER
All current and lower priority
interrupts are disabled.
Only a few targets/devices truly
support this masking option. For those
that don't, this setting is treated
the same as MaskingOption_SELF.
C SYNOPSIS
enum Hwi.RoutingMode |
|
Routing mode. ANY or NODE
values of type Hwi.RoutingMode
const Hwi.RoutingMode_NODE;
// Route interrupt to node specified by
affinity fields
const Hwi.RoutingMode_ALL;
// Route interrupt to all nodes
C SYNOPSIS
enum Hwi.Type |
|
Interrupt type. IRQ or FIQ
values of type Hwi.Type
const Hwi.Type_IRQ;
// IRQ interrupt
const Hwi.Type_FIQ;
// FIQ interrupt
C SYNOPSIS
struct Hwi.ExcContext |
|
Exception Context - Register contents at the time of an exception
var obj = new Hwi.ExcContext;
obj.threadHandle = Ptr ...
obj.threadStack = Ptr ...
obj.threadStackSize = SizeT ...
obj.x0 = Ptr ...
obj.x1 = Ptr ...
obj.x2 = Ptr ...
obj.x3 = Ptr ...
obj.x4 = Ptr ...
obj.x5 = Ptr ...
obj.x6 = Ptr ...
obj.x7 = Ptr ...
obj.x8 = Ptr ...
obj.x9 = Ptr ...
obj.x10 = Ptr ...
obj.x11 = Ptr ...
obj.x12 = Ptr ...
obj.x13 = Ptr ...
obj.x14 = Ptr ...
obj.x15 = Ptr ...
obj.x16 = Ptr ...
obj.x17 = Ptr ...
obj.x18 = Ptr ...
obj.x19 = Ptr ...
obj.x20 = Ptr ...
obj.x21 = Ptr ...
obj.x22 = Ptr ...
obj.x23 = Ptr ...
obj.x24 = Ptr ...
obj.x25 = Ptr ...
obj.x26 = Ptr ...
obj.x27 = Ptr ...
obj.x28 = Ptr ...
obj.x29 = Ptr ...
obj.x30 = Ptr ...
obj.sp = Ptr ...
obj.elr = Ptr ...
obj.spsr = Ptr ...
obj.esr = Ptr ...
C SYNOPSIS
struct Hwi.Gicc |
|
Generic Interrupt Controller CPU Interface. Symbol "Hwi_gicc" is
a physical device
var obj = new Hwi.Gicc;
obj.CTLR = UInt32 ...
// 0x0000 CPU Interface Control Register
obj.PMR = UInt32 ...
// 0x0004 Interrupt Priority Mask Register
obj.BPR = UInt32 ...
// 0x0008 Binary Point Register
obj.IAR = UInt32 ...
// 0x000C Interrupt Acknowledge Register
obj.EOIR = UInt32 ...
// 0x0010 End Of Interrupt Register
obj.RPR = UInt32 ...
// 0x0014 Running Priority Register
obj.HPPIR = UInt32 ...
// 0x0018 Highest Priority Pending Interrupt
Register
obj.ABPR = UInt32 ...
// 0x001C Aliased Binary Point Register
obj.AIAR = UInt32 ...
// 0x0020 Aliased IAR Register
obj.AEOIR = UInt32 ...
// 0x0024 Aliased EOI Register
obj.AHPPIR = UInt32 ...
// 0x0028 Aliased HPPI Register
obj.hole0 = UInt32[41] ...
// 0x002C-0x00CC
obj.APR0 = UInt32 ...
// 0x00D0 Active Priority Register
obj.hole1 = UInt32[3] ...
// 0x00D4-0x00DC
obj.NSAPR0 = UInt32 ...
// 0x00E0 Non-secure Active Priority Register
obj.hole2 = UInt32[6] ...
// 0x00E4-0x00F8
obj.IIDR = UInt32 ...
// 0x00FC CPU Interface Id Register
obj.hole3 = UInt32[960] ...
// 0x0100-0x0FFC
obj.DIR = UInt32 ...
// 0x1000 Deactivate Interrupt Register
C SYNOPSIS
struct Hwi.Gicd |
|
Generic Interrupt Controller Distributor. Symbol "Hwi_gicd" is
a physical device
var obj = new Hwi.Gicd;
obj.CTLR = UInt32 ...
// 0x0000 Distributor Control Register
obj.TYPER = UInt32 ...
// 0x0004 Interrupt Controller Type Register
obj.IIDR = UInt32 ...
// 0x0008 Distributor Implementor Id Register
obj.hole0 = UInt32[13] ...
// 0x000C-0x03C
obj.SETSPI_NSR = UInt32 ...
// 0x0040 Set SPI Register
obj.hole1 = UInt32 ...
// 0x0044
obj.CLRSPI_NSR = UInt32 ...
// 0x0048 Clear SPI Register
obj.hole2 = UInt32 ...
// 0x004C
obj.SETSPI_SR = UInt32 ...
// 0x0050 Set SPI Register
obj.hole3 = UInt32 ...
// 0x0054
obj.CLRSPI_SR = UInt32 ...
// 0x0058 Clear SPI Register
obj.hole4 = UInt32[9] ...
// 0x005C-0x007C
obj.IGROUPR = UInt32[32] ...
// 0x0080 Interrupt Group Registers
obj.ISENABLER = UInt32[32] ...
// 0x0100 Interrupt Set-Enable Registers
obj.ICENABLER = UInt32[32] ...
// 0x0180 Interrupt Clear-Enable Registers
obj.ISPENDR = UInt32[32] ...
// 0x0200 Interrupt Set-Pending Registers
obj.ICPENDR = UInt32[32] ...
// 0x0280 Interrupt Clear-Pending Registers
obj.ISACTIVER = UInt32[32] ...
// 0x0300 Interrupt Set-Active Registers
obj.ICACTIVER = UInt32[32] ...
// 0x0380 Interrupt Clear-Active Registers
obj.IPRIORITYR = UInt8[992] ...
// 0x0400 Interrupt Priority Registers
obj.hole5 = UInt32[8] ...
// 0x07E0-0x07FC
obj.ITARGETSR = UInt32[8] ...
// 0x0800 Interrupt Processor Targets
Register
obj.hole6 = UInt32[248] ...
// 0x0820-0x0BFC
obj.ICFGR = UInt32[64] ...
// 0x0C00 Interrupt Configuration Registers
obj.IGRPMODR = UInt32[32] ...
// 0x0D00 Interrupt Group Modifier Registers
obj.hole7 = UInt32[32] ...
// 0x0D80-0x0DFC
obj.NSACR = UInt32[64] ...
// 0x0E00 NonSecure Access Control Registers
obj.SGIR = UInt32 ...
// 0x0F00 Software Generated Interrupt
Register
obj.hole8 = UInt32[3] ...
// 0x0F04-0x0F0C
obj.CPENDSGIR = UInt32[4] ...
// 0x0F10 SGI Clear-Pending Registers
obj.SPENDSGIR = UInt32[4] ...
// 0x0F20 SGI Set-Pending Registers
obj.hole9 = UInt32[5172] ...
// 0x0F30-0x5FFC
obj.IROUTER = UInt64[992] ...
// 0x6000 Interrupt Routing Registers
obj.hole10 = UInt32[4160] ...
// 0x7F00-0xBFFC
obj.ESTATUSR = UInt32 ...
// 0xC000 Extended Status Register
obj.ERRTESTR = UInt32 ...
// 0xC004 Error Test Register
obj.hole11 = UInt32[31] ...
// 0xC008-0xC080
obj.SPISR = UInt32[30] ...
// 0xC084 SPI Status Registers
obj.hole12 = UInt32[4021] ...
// 0xC0FC-0xFFCC
obj.PIDR4 = UInt32 ...
// 0xFFD0 Peripheral ID4 Register
obj.PIDR5 = UInt32 ...
// 0xFFD4 Peripheral ID5 Register
obj.PIDR6 = UInt32 ...
// 0xFFD8 Peripheral ID6 Register
obj.PIDR7 = UInt32 ...
// 0xFFDC Peripheral ID7 Register
obj.PIDR0 = UInt32 ...
// 0xFFE0 Peripheral ID0 Register
obj.PIDR1 = UInt32 ...
// 0xFFE4 Peripheral ID1 Register
obj.PIDR2 = UInt32 ...
// 0xFFE8 Peripheral ID2 Register
obj.PIDR3 = UInt32 ...
// 0xFFEC Peripheral ID3 Register
obj.CIDR0 = UInt32 ...
// 0xFFF0 Component ID0 Register
obj.CIDR1 = UInt32 ...
// 0xFFF4 Component ID1 Register
obj.CIDR2 = UInt32 ...
// 0xFFF8 Component ID2 Register
obj.CIDR3 = UInt32 ...
// 0xFFFC Component ID3 Register
C SYNOPSIS
struct Hwi.Gicr |
|
Generic Interrupt Controller Redistributor Interface (RD_base).
Symbol "Hwi_gicr" is a physical device
var obj = new Hwi.Gicr;
obj.CTLR = UInt32 ...
// 0x0000 Redistributor Control Register
obj.IIDR = UInt32 ...
// 0x0004 Implementor Id Register
obj.TYPER = UInt32[2] ...
// 0x0008 Redistributor Type Register
obj.hole0 = UInt32 ...
// 0x0010
obj.WAKER = UInt32 ...
// 0x0014 Power Management Control Register
obj.hole1 = UInt32[22] ...
// 0x0018-0x006C
obj.PROPBASER = UInt32[2] ...
// 0x0070 LPI Config Table Base Register
obj.PENDBASER = UInt32[2] ...
// 0x0078 LPI Pending Table Base Register
C SYNOPSIS
struct Hwi.Gics |
|
Generic Interrupt Controller Redistributor Interface (SGI_base).
Symbol "Hwi_gics" is a physical device
var obj = new Hwi.Gics;
obj.hole0 = UInt32[32] ...
// 0x0000-0x007C
obj.IGROUPR0 = UInt32 ...
// 0x0080 Interrupt Group Register
obj.hole1 = UInt32[31] ...
// 0x0084-0x00FC
obj.ISENABLER0 = UInt32 ...
// 0x0100 Interrupt Set-Enable Register
obj.hole2 = UInt32[31] ...
// 0x0104-0x017C
obj.ICENABLER0 = UInt32 ...
// 0x0180 Interrupt Set-Enable Register
obj.hole3 = UInt32[31] ...
// 0x0184-0x01FC
obj.ISPENDR0 = UInt32 ...
// 0x0200 Interrupt Set-Enable Register
obj.hole4 = UInt32[31] ...
// 0x0204-0x027C
obj.ICPENDR0 = UInt32 ...
// 0x0280 Interrupt Set-Enable Register
obj.hole5 = UInt32[31] ...
// 0x0284-0x02FC
obj.ISACTIVER0 = UInt32 ...
// 0x0300 Interrupt Set-Enable Register
obj.hole6 = UInt32[31] ...
// 0x0304-0x037C
obj.ICACTIVER0 = UInt32 ...
// 0x0380 Interrupt Set-Enable Register
obj.hole7 = UInt32[31] ...
// 0x0384-0x03FC
obj.IPRIORITYR = UInt8[32] ...
// 0x0400 Interrupt Priority Registers
obj.hole8 = UInt32[504] ...
// 0x0420-0x0BFC
obj.ICFGR = UInt32[2] ...
// 0x0C00 Interrupt Configuration Registers
obj.hole9 = UInt32[62] ...
// 0x0C08-0x0CFC
obj.IGRPMODR0 = UInt32 ...
// 0x0D00 Interrupt Group Modifier Register
obj.hole10 = UInt32[63] ...
// 0x0D04-0x0DFC
obj.NSACR = UInt32 ...
// 0x0E00 NonSecure Access Control Register
C SYNOPSIS
struct Hwi.HookSet |
|
Hwi hook set type definition
var obj = new Hwi.HookSet;
obj.registerFxn = Void(*)(Int) ...
DETAILS
The functions that make up a hookSet have certain restrictions. They
cannot call any Hwi instance functions other than Hwi_getHookContext()
and Hwi_setHookContext(). For all practical purposes, they should treat
the Hwi_Handle passed to these functions as an opaque handle.
C SYNOPSIS
struct Hwi.IntAffinity |
|
Interrupt affinity type. Stores the hierarchical address (composed
of different affinity levels) that uniquely identifies the core or
processing element (PE) an interrupt is routed to
var obj = new Hwi.IntAffinity;
obj.aff0 = UInt8 ...
// Affinity level 0 - CoreId within cluster
obj.aff1 = UInt8 ...
// Affinity level 1 - Cluster Id
// Routing Mode - ALL or particular NODE
DETAILS
The routingMode field determines whether an interrupt is routed to
all nodes or a node identified by the affinity fields. This field
takes the value Hwi_RoutingMode_ANY and Hwi_RoutingMode_NODE.
If
BIOS.smpEnabled is true then,
all interrupts are forwarded to core 0 by default.
If
BIOS.smpEnabled is false then,
all interrupts are forwarded to all participating nodes.
CONSTRAINTS
This config param is ignored if
Core.bootMaster is
set to false.
C SYNOPSIS
struct Hwi.SgiIntAffinity |
|
Sgi interrupt affinity type. Stores affinity and routing mode
information that is used to determine which cores will the generated
SGI be routed to
var obj = new Hwi.SgiIntAffinity;
obj.targetList = UInt8 ...
// Bit map of target cores
obj.aff1 = UInt8 ...
// Identifies the target cluster
// Routing Mode - ALL or NODE target list
DETAILS
The routingMode field determines whether a generated SGI is routed to
all cores except the core generating the SGI (Hwi_RoutingMode_ALL) or
to list of target cores identified by the "targetList" and "aff1"
fields (Hwi_RoutingMode_NODE).
C SYNOPSIS
struct Hwi.StackInfo |
|
Structure contains Hwi stack usage info
var obj = new Hwi.StackInfo;
obj.hwiStackPeak = SizeT ...
obj.hwiStackSize = SizeT ...
obj.hwiStackBase = Ptr ...
DETAILS
Used by getStackInfo() and viewGetStackInfo() functions
C SYNOPSIS
config Hwi.A_badSGIIntNum // module-wide |
|
Assert raised when an interrupt number >= 16 is
passed to Hwi_raiseSGI() function
msg: "A_badSGIIntNum: SGI intNum should be <= 15."
};
C SYNOPSIS
config Hwi.BPR // module-wide |
|
GIC Binary Point Register value
Hwi.BPR = UInt undefined;
DETAILS
Defines the point at which the priority value fields split into
two parts, the group priority field and the sub-priority field.
When running in SECURE mode, BPR applies to Group 0 interrupts
and when running in NON-SECURE mode, BPR applies to Group 1
interrupts.
The group priority field determines interrupt preemption in case
of nested interrupts whereas sub-priority field is used to determine
priority within a group when multiple interrrupts belonging to the
same group are pending.
Valid BPR values are from 0-7 with the minimum value supported being
implementation defined and in the range 0-3.
-------------------------------------------------------
| BPR value | Group priority field | Sub-priority field |
-------------------------------------------------------
| 0 | [7:1] | [0] |
| 1 | [7:2] | [1:0] |
| 2 | [7:3] | [2:0] |
| 3 | [7:4] | [3:0] |
| 4 | [7:5] | [4:0] |
| 5 | [7:6] | [5:0] |
| 6 | [7] | [6:0] |
| 7 | No preemption | [7:0] |
-------------------------------------------------------
C SYNOPSIS
config Hwi.DEFAULT_INT_PRIORITY // module-wide |
|
Default Interrupt Priority
Hwi.DEFAULT_INT_PRIORITY = UInt undefined;
DETAILS
Set to one level higher than minimum supported priority.
C SYNOPSIS
config Hwi.E_alreadyDefined // module-wide |
|
Error raised when an attempt is made to create a Hwi
that has already been created
msg: "E_alreadyDefined: Hwi already defined, intnum: %d"
};
C SYNOPSIS
config Hwi.E_badIntNum // module-wide |
|
Error raised if an attempt is made to create a Hwi
with an interrupt number greater than Hwi_NUM_INTERRUPTS - 1
msg: "E_badIntNum, intnum: %d is out of range"
};
C SYNOPSIS
config Hwi.E_exception // module-wide |
|
Error raised when an exception occurs
msg: "E_exception: A hardware exception has occurred."
};
C SYNOPSIS
config Hwi.E_handleNotFound // module-wide |
|
Error raised when Hwi handle referenced in Hwi_delete()
is not found in the Hwi dispatch table
msg: "E_handleNotFound: Hwi handle not found: 0x%x"
};
C SYNOPSIS
config Hwi.E_undefined // module-wide |
|
Error raised when an undefined interrupt has fired
msg: "E_undefined: Hwi undefined, intnum: %d"
};
C SYNOPSIS
config Hwi.LD_end // module-wide |
|
Issued just after return from Hwi function (with interrupts disabled)
msg: "LD_end: hwi: 0x%x"
};
C SYNOPSIS
config Hwi.LM_begin // module-wide |
|
Issued just prior to Hwi function invocation (with interrupts disabled)
msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
};
C SYNOPSIS
config Hwi.MIN_INT_PRIORITY // module-wide |
|
Minimum Interrupt Priority
Hwi.MIN_INT_PRIORITY = UInt undefined;
C SYNOPSIS
config Hwi.NUM_PRIORITY_BITS // module-wide |
|
Number of Priority bits implemented
Hwi.NUM_PRIORITY_BITS = UInt undefined;
DETAILS
On OMAP543x running in non-secure mode, only most significant 4
priority bits are available for use. The least significant 4 bits
are always 0.
C SYNOPSIS
config Hwi.dispatcherAutoNestingSupport // module-wide |
|
Include interrupt nesting logic in interrupt dispatcher?
Hwi.dispatcherAutoNestingSupport = Bool true;
DETAILS
Default is true.
This option provides the user with the ability to optimize
interrupt dispatcher performance when support for interrupt
nesting is not required.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that manipulates interrupt mask
registers and enables and disables interrupts before and
after invoking the user's Hwi function.
Set this parameter to false if you don't need interrupts
enabled during the execution of your Hwi functions.
C SYNOPSIS
config Hwi.dispatcherIrpTrackingSupport // module-wide |
|
Controls whether the
dispatcher retains the interrupted thread's return address
Hwi.dispatcherIrpTrackingSupport = Bool true;
DETAILS
This option is enabled by default.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that keeps track of the interrupt's
return address and provide a small savings in interrupt latency.
The application can get an interrupt's most recent return
address using the
getIrp API.
C SYNOPSIS
config Hwi.dispatcherSwiSupport // module-wide |
|
Include Swi scheduling logic in interrupt dispatcher?
Hwi.dispatcherSwiSupport = Bool undefined;
DETAILS
Default is inherited from
BIOS.swiEnabled, which is true by default.
This option provides the user with the ability to optimize
interrupt dispatcher performance when it is known that Swis
will not be posted from any of their Hwi threads.
WARNING
Setting this parameter to false will disable the logic in
the interrupt dispatcher that invokes the Swi scheduler
prior to returning from an interrupt.
With this setting, Swis MUST NOT be posted from Hwi functions!
C SYNOPSIS
config Hwi.dispatcherTaskSupport // module-wide |
|
Include Task scheduling logic in interrupt dispatcher?
Hwi.dispatcherTaskSupport = Bool undefined;
DETAILS
Default is inherited from
BIOS.taskEnabled, which is true by default.
This option provides the user with the ability to optimize
interrupt dispatcher performance when it is known that no
Task scheduling APIs (ie
Semaphore_post()) will be executed from any of their Hwi threads.
Setting this parameter to false will disable the logic in
the interrupt dispatcher that invokes the Task scheduler
prior to returning from an interrupt.
C SYNOPSIS
config Hwi.enableDecode // module-wide |
|
Enable full exception decoding, default is true
Hwi.enableDecode = Bool true;
DETAILS
When enabled, the exception handler will fully
decode an exception and dump the registers to the
system console.
When set to false, only an Error is printed on the console.
In either case, the full exception context is always
saved and visible with ROV.
C SYNOPSIS
config Hwi.enableSecureMode // module-wide |
|
Security Mode
Hwi.enableSecureMode = Bool false;
DETAILS
This field specifies the MPU's security mode. The MPU's security mode
determines the type of accesses to the GIC i.e. if the MPU is in secure
mode, all accesses to the GIC are secure and if the MPU is in non-secure
mode, all accesses to the GIC are non-secure.
An exception to the above rule can be seen on certain devices like
Keystone 2, where all GIC acceses are secure irrespective of the MPU's
security state.
enableSecureMode should be set to true for such
devices.
C SYNOPSIS
config Hwi.sErrorExcHookFunc // module-wide |
|
User SError Exception hook function
DETAILS
Called just after the exception context has been initialized.
This function will be run on the ISR stack.
This function must run to completion.
It is called without any Task or Swi scheduling protection
and therefore can not call any functions that may cause a Swi or Task
scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
C SYNOPSIS
config Hwi.syncExcHookFunc // module-wide |
|
User Synchronous Exception hook function
DETAILS
Called just after the exception context has been initialized.
This function will be run on the ISR stack.
This function must run to completion.
It is called without any Task or Swi scheduling protection
and therefore can not call any functions that may cause a Swi or Task
scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
C SYNOPSIS
metaonly config Hwi.common$ // module-wide |
|
Common module configuration parameters
DETAILS
All modules have this configuration parameter. Its name
contains the '$' character to ensure it does not conflict with
configuration parameters declared by the module. This allows
new configuration parameters to be added in the future without
any chance of breaking existing modules.
metaonly config Hwi.excContextBuffer // module-wide |
|
User Exception Context Buffer Address
Hwi.excContextBuffer = Ptr[] undefined;
DETAILS
By default, when an exception occurs, an
ExcContext
structure is allocated on the ISR stack and filled in within the
exception handler.
If
excContextBuffer is initialized by the user, the
ExcContext structure will be placed at that address instead.
The buffer must be large enough to contain an
ExcContext
structure.
metaonly config Hwi.intAffinity // module-wide |
|
SMP Interrupt affinity mappings
Hwi.intAffinity = UInt8[] undefined;
DETAILS
In SMP mode, this array maps the interrupt number to the
core it is to be tied to. By default, all interrupts
are routed to Core0.
For example, to route Timer 1 (from the ti.sysbios.timers.dmtimer.Timer)
module interrupt to core 1 rather than core 0, add the following to
your config file:
var Hwi = xdc.useModule('ti.sysbios.family.arm.gicv3.Hwi');
Hwi.intAffinity[<intNum>] = 1;
CONSTRAINTS
Interrupt numbers below 32 are ignored. This config param only
allows routing interrupt numbers greater than or equal to #32.
metaonly config Hwi.intRouting // module-wide |
|
SMP Interrupt routing mappings
DETAILS
In SMP mode, this array maps the interrupt number to the
core or cores it is to be tied to. By default, all interrupts
are routed to Core0.
For example, to route Timer 1 (from the ti.sysbios.timers.dmtimer.Timer)
module interrupt to core 1 rather than core 0, add the following to
your config file:
var Hwi = xdc.useModule('ti.sysbios.family.arm.gicv3.Hwi');
Hwi.intRouting[<intNum>] = {aff0: 1, aff1: 0,
routingMode: Hwi.RoutingMode_NODE};
CONSTRAINTS
Interrupt numbers below 32 are ignored. This config param only
allows routing interrupt numbers greater than or equal to #32.
metaonly Hwi.addHookSet() // module-wide |
|
addHookSet is used in a config file to add a hook set (defined
by struct HookSet)
ARGUMENTS
hook
structure of type HookSet
DETAILS
HookSet structure elements may be omitted, in which case those
elements will not exist.
Instance Config Parameters |
|
var params = new Hwi.Params;
// Instance config-params object
params.arg = UArg 0;
// ISR function argument. Default is 0
params.enableInt = Bool true;
// Enable this interrupt when object is created? Default is true
params.eventId = Int -1;
// Interrupt event ID (Interrupt Selection Number)
// The interrupt controller is designed for priority based interrupts
params.priority = Int -1;
// Hwi instance interrupt priority
params.triggerSensitivity = UInt ~(0);
// Set an interrupt's trigger sensitivity
// Interrupt type (IRQ/FIQ). Default is IRQ
config Hwi.Params.arg // instance |
|
ISR function argument. Default is 0
var params = new Hwi.Params;
...
params.arg = UArg 0;
C SYNOPSIS
config Hwi.Params.enableInt // instance |
|
Enable this interrupt when object is created? Default is true
var params = new Hwi.Params;
...
params.enableInt = Bool true;
C SYNOPSIS
config Hwi.Params.eventId // instance |
|
Interrupt event ID (Interrupt Selection Number)
var params = new Hwi.Params;
...
params.eventId = Int -1;
DETAILS
Default is -1.
Not all targets/devices support this instance parameter.
On those that don't, this parameter is ignored.
C SYNOPSIS
config Hwi.Params.maskSetting // instance |
|
The interrupt controller is designed for priority based interrupts
var params = new Hwi.Params;
...
C SYNOPSIS
config Hwi.Params.priority // instance |
|
Hwi instance interrupt priority
var params = new Hwi.Params;
...
params.priority = Int -1;
DETAILS
The default value of -1 is used as a flag to indicate
the lowest (logical) device-specific priority value.
Not all targets/devices support this instance parameter.
On those that don't, this parameter is ignored.
Valid priorities are device dependent and their
nesting behaviors depend on the
BPR setting.
See the ARM GIC Architecture Specification v2.0 document for more
details.
C SYNOPSIS
config Hwi.Params.triggerSensitivity // instance |
|
Set an interrupt's trigger sensitivity
var params = new Hwi.Params;
...
params.triggerSensitivity = UInt ~(0);
DETAILS
2-bit field that configures the trigger sensitivity of an
interrupt.
On the Cortex-A15, all software generated interrupts (SGI)
are edge-triggered (b10) and all private peripheral interrupts (PPI)
are level-sensitive (b01). The trigger sensitivity of these
interrupt types cannot be changed.
For shared peripheral interrupts (SPI), the LSB of the bit-pair
is read only and is always 1. The MSB of the bit-pair can be
altered to change trigger sensitivity.
Possible bit-pair encodings for Cortex-A15 SPIs:
b01 Interrupt is active-High level-sensitive (default)
b11 Interrupt is rising edge-sensitive
For more information please refer section 4.3.13 on
Interrupt Configuration Registers (GICD_ICFGRn) in
ARM Generic Interrupt Controller Architecure Spec v2.0
CONSTRAINTS
This Hwi param is ignored if
Core.bootMaster is
set to false.
C SYNOPSIS
config Hwi.Params.type // instance |
|
Interrupt type (IRQ/FIQ). Default is IRQ
var params = new Hwi.Params;
...
NOTE
FIQs are only supported when
enableSecureMode is set to
true.
C SYNOPSIS
Static Instance Creation |
|
// Allocate instance config-params
params.config = ...
// Assign individual configs
var inst = Hwi.create(Int intNum, Void(*)(UArg) hwiFxn, params);
// Create an instance-object
ARGUMENTS
intNum
interrupt number
hwiFxn
pointer to ISR function
params
per-instance config params, or NULL to select default values (target-domain only)
eb
active error-handling block, or NULL to select default policy (target-domain only)
DETAILS
A Hwi dispatcher table entry is created and filled with the
function specified by the fxn parameter and the attributes
specified by the params parameter.
If params is NULL, the Hwi's dispatcher properties are assigned a
default set of values. Otherwise, the following properties
are specified by a structure of type Hwi_Params.
- The arg element is a generic argument that is passed to the plugged
function as its only parameter. The default value is 0.
- The enableInt element determines whether the interrupt should be
enabled in the IER by create.
- The maskSetting element defines the dispatcherAutoNestingSupport
behavior of the interrupt.
Hwi_create returns a pointer to the created Hwi object.