var Cache = xdc.useModule('ti.sysbios.family.arm.arm9.Cache');
    var Mmu = xdc.useModule('ti.sysbios.family.arm.arm9.Mmu');

    // Enable the cache
    Cache.enableCache = true;

    // Enable the MMU (Required for L1 data caching)
    Mmu.enableMMU = true;

    // descriptor attribute structure
    var attrs = {
        type: Mmu.FirstLevelDesc_SECTION,  // SECTION descriptor
        bufferable: true,                  // bufferable
        cacheable: true,                   // cacheable
        imp: 1,                            // implementation defined
        domain: 0,                         // domain between 0-15
        accPerm: 3,                        // read/write permission
    };

    // Set the descriptor for each entry in the address range
    for (var i=0xC3000000; i < 0xC4000000; i = i + 0x00100000) {
        // Each 'SECTION' descriptor entry spans a 1MB address range
        Mmu.setFirstLevelDescMeta(i, i, attrs);
    }

    var memmap = Program.cpu.memoryMap;
    var DDR = null;

    // Find DDR in memory map
    for (var i=0; i < memmap.length; i++) {
        if (memmap[i].name == "DDR") {
            DDR = memmap[i];
        }
    }

    // Place the MMU table in the DDR memory segment if it exists
    if (DDR != null) {
        var sectionName = "ti.sysbios.family.arm.arm9.mmuTableSection";
        Program.sectMap[sectionName] = new Program.SectionSpec();
        Program.sectMap[sectionName].type = "NOINIT";
        Program.sectMap[sectionName].loadSegment = "DDR";
    }
    else {
        print("No DDR memory segment was found");
    }

    #define MMU_LEVEL2DESC_SMALLPAGE    0x2
    #define MMU_LEVEL2DESC_BUFFERABLE   0x4
    #define MMU_LEVEL2DESC_CACHEABLE    0x8

    #pragma DATA_ALIGN(mmuL2Table, 4096);    // align to 4KB

    UInt32 mmuL2Table[256];   // each level 2 descriptor specifies a 4KB block

    Void main(Int argc, Char * argv[])
    {
        Mmu_FirstLevelDescAttrs attrs;
        Int i;

        // initialize the second level descriptors
        for (i=0; i < 256; i++) {
             mmuL2Table[i] = 0;
        }

        // change the address starting at 0xFFFEE000 to be a small page
        mmuL2Table[0xEE] = 0xFFFEE000 | // set the physical address
            MMU_LEVEL2DESC_SMALLPAGE |  // set descriptor to small page (4KB)
            0xFF0;                      // set Access Permission bits to 1

        // change the address starting at 0xFFFEF000 to be a small page
        mmuL2Table[0xEF] = 0xFFFEF000 | // set the physical address
            MMU_LEVEL2DESC_SMALLPAGE |  // set descriptor to small page (4KB)
            0xFF0;                      // set Access Permission bits to 1

        // change the address starting at 0xFFFF0000 to be a small page
        mmuL2Table[0xF0] = 0xFFFF0000 | // set the physical address
            MMU_LEVEL2DESC_SMALLPAGE |  // set descriptor to small page (4KB)
            MMU_LEVEL2DESC_CACHEABLE |  // set cacheable bit to true
            MMU_LEVEL2DESC_BUFFERABLE | // set bufferable bit to true
            0xFF0;                      // set Access Permission bits to 1

        // first level descriptor properties
        attrs.type = Mmu_FirstLevelDesc_COARSE; // set to a coarse descriptor
        attrs.imp = 1;                          // defined to be 1 for ARM9
        attrs.domain = 0;                       // set domain to 0

        // Set the first level descriptor for the virtual address 0xFFFF0000.
        Mmu_setFirstLevelDesc((Ptr)0xFFFF0000, &mmuL2Table, &attrs);

        // enable MMU
        Mmu_enable();

        BIOS_start();
    }