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32 33 34
35
36 package ti.sysbios.family.arm.a15.tci66xx;
37
38 import xdc.runtime.Assert;
39 import xdc.runtime.Error;
40
41 /*!
42 * ======== CpIntc ========
43 * Chip-level Interrupt Controller Manager
44 *
45 * This module manages the CP_INTC hardware. This module supports enabling
46 * and disabling of both system and host interrupts. This module also
47 * supports mapping system interrupts to host interrupts and host interrupts
48 * to Hwis. These functions are supported statically and during runtime for
49 * CP_INTC connected to the ARM generic interrupt controller. There is a
50 * dispatch function for handling ARM hardware interrupts triggered by a system
51 * interrupt. The Global Enable Register is enabled by default in the module
52 * startup function.
53 *
54 * System interrupts are those interrupts generated by a hardware module
55 * in the system. These interrupts are inputs into CP_INTC.
56 * Host interrupts are the output interrupts of CP_INTC.
57 * There is a one-to-one mapping between channels and host interrupts
58 * therefore, the term "host interrupt" is also used for channels.
59 *
60 * @p(code)
61 * +------------+------------+
62 * ------->|\ Channel | Channel |
63 * | \ Mapping | to |
64 * ------->|\ \ | Host |
65 * | \ \ | Interrupt |
66 * ------->|\ \ \ | direct | Host
67 * | \ \ \ | mapping | Interrupts
68 * ------->|\ \ \ \ | | +-------+
69 * | \ \ \ \ |____________|___________| |
70 * System ------->|\ \ \ \ \ /| | | |
71 * Interrupts : | \ \ \ \ \/ |____________|___________| |
72 * : | \ \ \ \/\/| | | |
73 * : | \ \ \/\/\|____________|___________| |
74 * : | \ \/\/\/| | | |
75 * : | \/\/\/\|____________|___________| ARM |
76 * : | /\/\/\/| | | GIC |
77 * : | / /\/\/\|____________|___________| |
78 * : | / / /\/\/| | | |
79 * : | / / / /\/\|____________|___________| |
80 * : | / / / / /\ | | | |
81 * ------->|/ / / / / \|____________|___________| |
82 * | / / / / | | | |
83 * ------->|/ / / / | | +-------+
84 * | / / / | |
85 * ------->|/ / / | |
86 * | / / | |
87 * ------->|/ / | |
88 * | / | |
89 * ------->|/ | |
90 * +------------+------------+
91 * @p
92 *
93 * This modules does not support prioritization, nesting, and vectorization.
94 *
95 * An example of using CpIntc during runtime to plug the ISR handler for
96 * System interrupt 15 mapped to Host interrupt 18.
97 *
98 * @p(code)
99 *
100 * Int intNum;
101 * Hwi_Params params;
102 * Error_Block eb;
103 *
104 * // Initialize the error block
105 * Error_init(&eb);
106 *
107 * // Map system interrupt 15 to Host interrupt 18
108 * CpIntc_mapSysIntToHostInt(15, 18);
109 *
110 * // Plug the function and argument for System interrupt 15 then enable it
111 * CpIntc_dispatchPlug(15, &myEvent15Fxn, 15, TRUE);
112 *
113 * // Enable Host interrupt 18
114 * CpIntc_enableHostInt(18);
115 *
116 * // Get the ARM Hwi interrupt number associated with Host interrupt 18
117 * intNum = CpIntc_getIntNum(18);
118 *
119 * // Initialize the Hwi parameters
120 * Hwi_Params_init(¶ms);
121 *
122 * // The arg must be set to the key returned by CpIntc_getHostIntKey()
123 * params.arg = (UInt)CpIntc_getHostIntKey(18);
124 *
125 * // Enable the interrupt vector
126 * params.enableInt = TRUE;
127 *
128 * // Create the Hwi on interrupt intNum then specify 'CpIntc_dispatch'
129 * // as the handler function.
130 * Hwi_create(intNum, &CpIntc_dispatch, ¶ms, &eb);
131 *
132 * @p
133 *
134 * An example of using CpIntc statically to plug the ISR handler for System
135 * interrupt 201 mapped to Host interrupt 90.
136 *
137 * *.cfg code
138 * @p(code)
139 * var Hwi = xdc.useModule('ti.sysbios.family.arm.gic.Hwi');
140 * var CpIntc = xdc.useModule('ti.sysbios.family.arm.a15.tci66xx.CpIntc');
141 *
142 * // Map System interrupt 201 to Host interrupt 90
143 * CpIntc.sysInts[201].fxn = "&mySysIntFxn";
144 * CpIntc.sysInts[201].arg = 90;
145 * CpIntc.sysInts[201].hostInt = 90;
146 * CpIntc.sysInts[201].enable = true;
147 *
148 * var intNum = CpIntc.getIntNumMeta(90);
149 * var params = new Hwi.Params();
150 * params.arg = CpIntc.getHostIntKeyMeta(90);
151 * Hwi.create(intNum, CpIntc.dispatch, params);
152 * @p
153 *
154 * @a(NOTE)
155 * If multiple system interrupts are mapped to the same host interrupt, the
156 * performance may deteriorate as the CpIntc_dispatch() function has to
157 * scan all SysInt to HostInt map registers to determine which system
158 * interrupts are mapped to the currently active host interrupt.
159 *
160 * @p(html)
161 * <h3> Calling Context </h3>
162 * <table border="1" cellpadding="3">
163 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
164 *
165 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
166 * <!-- -->
167 * <tr><td> {@link #clearSysInt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
168 * <tr><td> {@link #disableAllHostInts} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
169 * <tr><td> {@link #disableHostInt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
170 * <tr><td> {@link #dispatch} </td><td> Y </td><td> N </td><td> N </td><td> N </td><td> N </td></tr>
171 * <tr><td> {@link #disableHostInt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
172 * <tr><td> {@link #dispatchPlug} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
173 * <tr><td> {@link #enableAllHostInts} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
174 * <tr><td> {@link #enableHostInt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
175 * <tr><td> {@link #enableSysInt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
176 * <tr><td> {@link #getHostInt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
177 * <tr><td> {@link #getHostIntKey} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
178 * <tr><td> {@link #getIntNum} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
179 * <tr><td> {@link #mapSysIntToHostInt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
180 * <tr><td> {@link #postSysInt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
181 * <tr><td colspan="6"> Definitions: <br />
182 * <ul>
183 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
184 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
185 * <li> <b>Task</b>: API is callable from a Task thread. </li>
186 * <li> <b>Main</b>: API is callable during any of these phases: </li>
187 * <ul>
188 * <li> In your module startup after this module is started (e.g. CpIntc_Module_startupDone() returns TRUE). </li>
189 * <li> During xdc.runtime.Startup.lastFxns. </li>
190 * <li> During main().</li>
191 * <li> During BIOS.startupFxns.</li>
192 * </ul>
193 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
194 * <ul>
195 * <li> During xdc.runtime.Startup.firstFxns.</li>
196 * <li> In your module startup before this module is started (e.g. CpIntc_Module_startupDone() returns FALSE).</li>
197 * </ul>
198 * </ul>
199 * </td></tr>
200 *
201 * </table>
202 * @p
203 */
204
205 @DirectCall
206 @ModuleStartup
207
208 module CpIntc
209 {
210 /*!
211 * ======== SysIntsView ========
212 * @_nodoc
213 */
214 metaonly struct SysIntsView {
215 UInt systemInt;
216 UInt16 hostInt;
217 String fxn;
218 UArg arg;
219 Bool enabled;
220 };
221
222 /*!
223 * ======== rovViewInfo ========
224 * @_nodoc
225 */
226 @Facet
227 metaonly config xdc.rov.ViewInfo.Instance rovViewInfo =
228 xdc.rov.ViewInfo.create({
229 viewMap: [
230 ['SysInts',
231 {
232 type: xdc.rov.ViewInfo.MODULE_DATA,
233 viewInitFxn: 'viewInitSystemInts',
234 structName: 'SysIntsView'
235 }
236 ]
237 ]
238 });
239
240 /*! CpIntc dispatcher function type definition. */
241 typedef Void (*FuncPtr)(UArg);
242
243 /*!
244 * Common Platform Interrupt Controller.
245 */
246 struct RegisterMap {
247 UInt32 REV; /*! 0x00 Revision Register */
248 UInt32 CR; /*! 0x04 Control Register */
249 UInt32 RES_08; /*! 0x08 reserved */
250 UInt32 HCR; /*! 0x0C Host Control Register */
251 UInt32 GER; /*! 0x10 Global Enable Register */
252 UInt32 RES_14; /*! 0x14 reserved */
253 UInt32 RES_18; /*! 0x18 reserved */
254 UInt32 GNLR; /*! 0x1C Global Nesting Level Register */
255 UInt32 SISR; /*! 0x20 Status Index Set Register */
256 UInt32 SICR; /*! 0x24 Status Index Clear Register */
257 UInt32 EISR; /*! 0x28 Enable Index Set Register */
258 UInt32 EICR; /*! 0x2C Enable Index Clear Register */
259 UInt32 GWER; /*! 0x30 Global Wakeup Enable Register */
260 UInt32 HIEISR; /*! 0x34 Host Int Enable Index Set Register */
261 UInt32 HIDISR; /*! 0x38 Host Int Disable Index Set Register */
262 UInt32 RES_3C; /*! 0x3C reserved */
263 UInt32 PPR; /*! 0x40 Pacer Prescale Register */
264 UInt32 RES_44; /*! 0x44 reserved */
265 UInt32 RES_48; /*! 0x48 reserved */
266 UInt32 RES_4C; /*! 0x4C reserved */
267 Ptr *VBR; /*! 0x50 Vector Base Register */
268 UInt32 VSR; /*! 0x54 Vector Size Register */
269 Ptr VNR; /*! 0x58 Vector Null Register */
270 UInt32 RES_5C[9]; /*! 0x5C-0x7C reserved */
271 Int32 GPIR; /*! 0x80 Global Prioritized Index Register */
272 Ptr *GPVR; /*! 0x84 Global Prioritized Vector Register */
273 UInt32 RES_88; /*! 0x88 reserved */
274 UInt32 RES_8C; /*! 0x8C reserved */
275 UInt32 GSIER; /*! 0x90 Global Secure Interrupt Enable Register */
276 UInt32 SPIR; /*! 0x94 Secure Prioritized Index Register */
277 UInt32 RES_98[26]; /*! 0x98-0xFC reserved */
278 UInt32 PPMR[64]; /*! 0x100-0x1FC Pacer Parameter/Map Registers */
279 UInt32 SRSR[32]; /*! 0x200-0x27C Status Raw/Set Registers */
280 UInt32 SECR[32]; /*! 0x280-0x2FC Status Enabled/Clear Registers */
281 UInt32 ESR[32]; /*! 0x300-0x37C Enable Set Registers */
282 UInt32 ECR[32]; /*! 0x380-0x3FC Enable Clear Registers */
283 UInt8 CMR[1024]; /*! 0x400-0x7FC Channel Map Registers */
284 UInt8 HIMR[256]; /*! 0x800-0x8FC Host Interrupt Map Registers */
285 UInt32 HIPIR[256]; /*! 0x900-0xCFC Host Interrupt Pri Index
286 Registers */
287 UInt32 PR[32]; /*! 0xD00-0xD7C Polarity Registers */
288 UInt32 TR[32]; /*! 0xD80-0xDFC Type Registers */
289 UInt32 WER[64]; /*! 0xE00-0xEFC Wakeup Enable Registers */
290 UInt32 DSR[64]; /*! 0xF00-0xFFC Debug Select Registers */
291 UInt32 SER[32]; /*! 0x1000-0x107C Secure Enable Registers */
292 UInt32 SDR[32]; /*! 0x1080-0x10FC Secure Disable Registers */
293 UInt32 HINLR[256]; /*! 0x1100-0x14FC Host Interrupt Nesting Level
294 Registers */
295 UInt32 HIER[8]; /*! 0x1500-0x151F Host Interrupt Enable Registers */
296 UInt32 RES1520[56]; /*! 0x1520-0x15FC Reserved */
297 Ptr *HIPVR[256]; /*! 0x1600-0x19FC Host Interrupt Prioritized
298 Vector */
299 UInt32 RES1A00[384];/*! 0x1A00-0x1FFC Reserved */
300 };
301
302 /*!
303 * System Interrupt Object.
304 */
305 metaonly struct SysIntObj {
306 FuncPtr fxn;
307 UArg arg;
308 UInt16 hostInt;
309 Bool enable;
310 };
311
312 /*!
313 * ======== A_sysIntOutOfRange ========
314 * Assert raised when system interrupt is out of range.
315 */
316 config Assert.Id A_sysIntOutOfRange = {
317 msg: "A_sysIntOutOfRange: Sys Int number passed is invalid."
318 };
319
320 /*!
321 * Error raised when an unplugged system interrupt is executed.
322 */
323 config Error.Id E_unpluggedSysInt = {
324 msg: "E_unpluggedSysInt: System Interrupt# %d is unplugged"
325 };
326
327 /*!
328 * ======== sysInts ========
329 * Used for configuring the system interrupts.
330 *
331 * During static configuration this array can be used to configure
332 * the function to execute when a system interrupt is triggered,
333 * the arg to the function, the host interrupt to which the system
334 * interrupt is mapped too, and whether to enable the system interrupt.
335 */
336 metaonly config SysIntObj sysInts[];
337
338 /*!
339 * ======== getHostIntKeyMeta ========
340 * Returns a key that should be passed as an argument to CpIntc_dispatch()
341 *
342 * If invalid host interrupt number is passed, the value -1 will be
343 * returned.
344 *
345 * @param(intNum) Host interrupt number
346 * @b(returns) Key
347 */
348 metaonly Int getHostIntKeyMeta(UInt hostInt);
349
350 /*!
351 * ======== getIntNumMeta ========
352 * Returns the Hwi interrupt number associated with the host
353 * interrupt
354 *
355 * If no ARM interrupt is associated with the host interrupt, the value
356 * -1 will be returned.
357 *
358 * @param(hostInt) host interrupt number
359 * @b(returns) ARM interrupt number
360 *
361 * @a(Note)
362 * ARM CorePac interrupt number 0 to N in Keystone2 reference manual
363 * maps to ARM GIC interrupt number 32 to (N + 32).
364 *
365 * This function returns the ARM GIC interrupt number.
366 */
367 metaonly Int getIntNumMeta(UInt hostInt);
368
369 /*!
370 * ======== clearSystInt ========
371 * Clears the system interrupt.
372 *
373 * Writes the system interrupt number to the System Interrupt
374 * Status Indexed Clear Register.
375 *
376 * @param(sysInt) system interrupt number
377 */
378 Void clearSysInt(UInt sysInt);
379
380 /*!
381 * ======== disableAllHostInts ========
382 * Disables all host interrupts.
383 *
384 * Writes a 0 to the Global Enable Register. It does not
385 * override the individual host interrupt enable/disable bits.
386 */
387 Void disableAllHostInts();
388
389 /*!
390 * ======== disableHostInt ========
391 * Disables the host interrupt.
392 *
393 * Writes the host interrupt number to the Host Interrupt
394 * Enable Index Clear Register.
395 *
396 * @param(hostInt) host interrupt number
397 */
398 Void disableHostInt(UInt hostInt);
399
400 /*!
401 * ======== disableSysInt ========
402 * Disables the system interrupt.
403 *
404 * Writes the system interrupt number to the System Interrupt
405 * Enable Indexed Clear Register.
406 *
407 * @param(sysInt) system interrupt number
408 */
409 Void disableSysInt(UInt sysInt);
410
411 /*!
412 * ======== dispatch ========
413 * The Interrupt service routine handler for CP_INTC events.
414 *
415 * It is used internally, but can also be used by the user.
416 *
417 * @param(hostInt) host interrupt number
418 */
419 Void dispatch(UArg hostInt);
420
421 /*!
422 * ======== dispatchPlug ========
423 * Configures a CpIntc ISR dispatch entry.
424 *
425 * Plugs the function and argument for the specified system interrupt.
426 * Also enables the system interrupt if 'unmask' is set to 'true'.
427 * Function does not map the system interrupt to a Hwi interrupt.
428 *
429 * @param(sysInt) system interrupt number
430 * @param(fxn) function
431 * @param(arg) argument to function
432 * @param(unmask) bool to unmask interrupt
433 */
434 Void dispatchPlug(UInt sysInt, FuncPtr fxn, UArg arg, Bool unmask);
435
436 /*!
437 * ======== enableAllHostInts ========
438 * Enables all host interrupts.
439 *
440 * Writes a 1 to the Global Enable Register. It does not
441 * override the individual host interrupt enable/disable bits.
442 */
443 Void enableAllHostInts();
444
445 /*!
446 * ======== enableHostInt ========
447 * Enables the host interrupt.
448 *
449 * Writes the host interrupt number to the Host Interrupt
450 * Enable Indexed Set Register.
451 *
452 * @param(hostInt) host interrupt number
453 */
454 Void enableHostInt(UInt hostInt);
455
456 /*!
457 * ======== enableSysInt ========
458 * Enables the system interrupt.
459 *
460 * Writes the system interrupt number to the System Interrupt
461 * Enable Indexed Set Register.
462 *
463 * @param(sysInt) system interrupt number
464 */
465 Void enableSysInt(UInt sysInt);
466
467 /*!
468 * ======== getIntNum ========
469 * Returns the Hwi interrupt number associated with the host
470 * interrupt
471 *
472 * If no ARM interrupt is associated with the host interrupt, the value
473 * -1 will be returned.
474 *
475 * @param(hostInt) host interrupt number
476 * @b(returns) ARM interrupt number
477 *
478 * @a(Note)
479 * ARM CorePac interrupt number 0 to N in Keystone2 reference manual
480 * maps to ARM GIC interrupt number 32 to (N + 32).
481 *
482 * This function returns the ARM GIC interrupt number.
483 */
484 Int getIntNum(UInt hostInt);
485
486 /*!
487 * ======== getHostInt ========
488 * Returns the host interrupt associated with the ARM CorePac interrupt
489 *
490 * If no host interrupt is associated with the ARM interrupt, the value
491 * -1 will be returned.
492 *
493 * @param(intNum) ARM CorePac interrupt number
494 * @b(returns) Host interrupt number
495 */
496 Int getHostInt(UInt intNum);
497
498 /*!
499 * ======== getHostIntKey ========
500 * Returns a key that should be passed as an argument to CpIntc_dispatch()
501 *
502 * If invalid host interrupt number is passed, the value -1 will be
503 * returned.
504 *
505 * @param(intNum) Host interrupt number
506 * @b(returns) Key
507 */
508 Int getHostIntKey(UInt hostInt);
509
510 /*!
511 * ======== mapSysIntToHostInt ========
512 * Maps a system interrupt to a host interrupt.
513 *
514 * Writes the Channel Map Register to map a system interrupt to a
515 * channel. There is a 1 to 1 mapping between channels and
516 * host interrupts.
517 *
518 * @param(sysInt) system interrupt number
519 * @param(hostInt) host interrupt number
520 */
521 Void mapSysIntToHostInt(UInt sysInt, UInt hostInt);
522
523 /*!
524 * ======== postSysInt ========
525 * Triggers the system interrupt.
526 *
527 * Writes the system interrupt number to the System Interrupt
528 * Status Index Set Register. Used for diagnostic and test purposes
529 * only.
530 *
531 * @param(sysInt) system interrupt number
532 */
533 Void postSysInt(UInt sysInt);
534
535 /*!
536 * @_nodoc
537 * ======== unused ========
538 * Default handler function registered for all unplugged system
539 * interrupts.
540 */
541 Void unused(UArg arg);
542
543 internal:
544
545 546 547
548 struct HostIntObj {
549 UInt16 hostInt;
550 UInt16 sysInt;
551
552 };
553
554
555 metaonly config UInt32 baseAddr;
556
557
558 config UInt32 numSysInts;
559
560
561 config UInt32 numArmInts;
562
563
564 config Int numStatusRegs;
565
566
567 config UInt16 sysIntToHostInt[];
568
569
570 config UInt16 hostIntToArmIntNum[];
571
572
573 config UInt16 intNum[];
574
575 struct DispatchTabElem {
576 FuncPtr fxn;
577 UArg arg;
578 };
579
580 struct Module_State {
581 volatile RegisterMap *controller;
582 Bits32 initSIER[];
583 HostIntObj hostIntToSysInt[];
584 DispatchTabElem dispatchTab[];
585 };
586 }