1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== TMS320CF761990.xdc ========
35 *
36 */
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== TMS320CF761990 ========
41 * The C64P device data sheet module.
42 *
43 * This module implements the xdc.platform.ICpuDataSheet interface and is
44 * used by platforms to obtain "data sheet" information about this device.
45 */
46 metaonly module TMS320CF761990 inherits ti.catalog.ICpuDataSheet
47 {
48
49 config long cacheSizeL1[string] = [
50 ["0k", 0x0000],
51 ["4k", 0x1000],
52 ["8k", 0x2000],
53 ["16k", 0x4000],
54 ["32k", 0x8000],
55 ];
56
57 config long cacheSizeL2[string] = [
58 ["0k", 0x00000],
59 ["32k", 0x08000],
60 ["64k", 0x10000]
61 ];
62
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode',{desc:"L1P Cache",
65 base: 0x11E08000,
66 map : [["0k",0x0000],
67 ["4k",0x1000],
68 ["8k",0x2000],
69 ["16k",0x4000],
70 ["32k",0x8000]],
71 defaultValue: "32k",
72 memorySection: "L1PSRAM"}],
73
74 ['l1DMode',{desc:"L1D Cache",
75 base: 0x11F04000,
76 map : [["0k",0x0000],
77 ["4k",0x1000],
78 ["8k",0x2000],
79 ["16k",0x4000],
80 ["32k",0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}],
83
84 ['l2Mode',{desc:"L2 Cache",
85 base: 0x11800000,
86 map : [["0k",0x0000],
87 ["32k",0x8000],
88 ["64k",0x10000]],
89 defaultValue: "0k",
90 memorySection: "IRAM"}],
91
92 ];
93
94 instance:
95 override config int minProgUnitSize = 1;
96 override config int minDataUnitSize = 1;
97 override config int dataWordSize = 4;
98
99 override config string cpuCore = "F761990";
100 override config string isa = "64P";
101 override config string cpuCoreRevision = "1.0";
102
103 config xdc.platform.IPlatform.Memory memMap[string] = [
104 ["IRAM", {
105 comment: "Internal 64KB L2 UMAP0 memory",
106 name: "IRAM",
107 base: 0x11800000,
108 len: 0x00010000,
109 space: "code/data",
110 access: "RWX"
111 }],
112
113 ["L1PSRAM", {
114 comment: "Internal 32KB L1 program memory",
115 name: "L1PSRAM",
116 base: 0x11E08000,
117 len: 0x00008000,
118 space: "code",
119 access: "RWX"
120 }],
121
122 ["L1DSRAM", {
123 comment: "Internal 80KB L1 data memory",
124 name: "L1DSRAM",
125 base: 0x11F04000,
126 len: 0x00014000,
127 space: "data",
128 access: "RW"
129 }],
130
131 ["ARM_RAM0", {
132 comment: "Internal ARM RAM instruction memory",
133 name: "ARM_RAM0",
134 base: 0x02000000,
135 len: 0x00008000,
136 space: "code",
137 access: "RWX"
138 }],
139
140 ["ARM_RAM1", {
141 comment: "Internal ARM RAM data memory",
142 name: "ARM_RAM1",
143 base: 0x02008000,
144 len: 0x00004000,
145 space: "data",
146 access: "RW"
147 }],
148 ];
149 };