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33 34 35 36
37
38 package ti.catalog.c6000;
39
40 /*!
41 * ======== TMS320CDM6431 ========
42 * The DM6431 device data sheet module.
43 *
44 * This module implements the xdc.platform.ICpuDataSheet interface and is
45 * used by platforms to obtain "data sheet" information about this device.
46 */
47 metaonly module TMS320CDM6431 inherits ti.catalog.ICpuDataSheet
48 {
49 config long cacheSizeL1[string] = [
50 ["0k", 0x0000],
51 ["4k", 0x1000],
52 ["8k", 0x2000],
53 ["16k", 0x4000],
54 ["32k", 0x8000]
55 ];
56
57 config long cacheSizeL2[string] = [
58 ["0k", 0x00000],
59 ["32k", 0x08000],
60 ["64k", 0x10000]
61 ];
62
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode',{desc:"L1P Cache",
65 base: 0x10E08000,
66 map : [["0k",0x0000],
67 ["4k",0x1000],
68 ["8k",0x2000],
69 ["16k",0x4000],
70 ["32k",0x8000]],
71 defaultValue: "32k",
72 memorySection: "L1PSRAM"}],
73
74 ['l1DMode',{desc:"L1D Cache",
75 base: 0x10F10000,
76 map : [["0k",0x0000],
77 ["4k",0x1000],
78 ["8k",0x2000],
79 ["16k",0x4000],
80 ["32k",0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}],
83
84 ['l2Mode',{desc:"L2 Cache",
85 base: 0x10810000,
86 map : [["0k",0x0000],
87 ["32k",0x8000],
88 ["64k",0x10000]],
89 defaultValue: "0k",
90 memorySection: "IRAM"}],
91 ];
92
93 instance:
94
95 override config string cpuCore = "64x+";
96 override config string isa = "64P";
97 override config string cpuCoreRevision = "1.0";
98
99 override config int minProgUnitSize = 1;
100 override config int minDataUnitSize = 1;
101 override config int dataWordSize = 4;
102
103 /*!
104 * ======== memMap ========
105 * The default memory map for this device
106 */
107 config xdc.platform.IPlatform.Memory memMap[string] = [
108 ["IRAM", {
109 comment: "Internal 64KB L2 RAM/CACHE in UMAP0 memory",
110 name: "IRAM",
111 base: 0x10810000,
112 len: 0x00010000,
113 space: "code/data",
114 access: "RWX"
115 }],
116
117 ["L1PSRAM", {
118 comment: "Internal 32KB RAM/CACHE L1 program memory",
119 name: "L1PSRAM",
120 base: 0x10E08000,
121 len: 0x00008000,
122 space: "code",
123 access: "RWX"
124 }],
125
126 ["L1DSRAM", {
127 comment: "Internal 32KB RAM/CACHE L1 data memory",
128 name: "L1DSRAM",
129 base: 0x10F10000,
130 len: 0x00008000,
131 space: "data",
132 access: "RW"
133 }],
134 ];
135 };