1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== TMS320C66AK2E02.xdc ========
35 *
36 */
37
38 package ti.catalog.c6000;
39
40 metaonly module TMS320C66AK2E02 inherits ti.catalog.ICpuDataSheet
41 {
42 /* These are the available sizes for L1 caches */
43 config long cacheSizeL1[string] = [
44 ["0k", 0x0000],
45 ["4k", 0x1000],
46 ["8k", 0x2000],
47 ["16k", 0x4000],
48 ["32k", 0x8000],
49 ];
50
51 /* These are the available sizes for L2 cche */
52 config long cacheSizeL2[string] = [
53 ["0k", 0x000000],
54 ["32k", 0x008000],
55 ["64k", 0x010000],
56 ["128k", 0x020000],
57 ["256k", 0x040000],
58 ["512k", 0x080000]
59 ];
60
61 /* This is used by platform wizard for setting default cache sizes */
62 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
63 ['l1PMode', {
64 desc:"L1P Cache",
65 base: 0x00E00000,
66 map : [
67 ["0k",0x0000],
68 ["4k",0x1000],
69 ["8k",0x2000],
70 ["16k",0x4000],
71 ["32k",0x8000]
72 ],
73 defaultValue: "32k",
74 memorySection: "L1PSRAM"
75 }],
76 ['l1DMode', {
77 desc:"L1D Cache",
78 base: 0x00F00000,
79 map : [
80 ["0k",0x0000],
81 ["4k",0x1000],
82 ["8k",0x2000],
83 ["16k",0x4000],
84 ["32k",0x8000]
85 ],
86 defaultValue: "32k",
87 memorySection: "L1DSRAM"
88 }],
89 ['l2Mode', {
90 desc:"L2 Cache",
91 base: 0x00800000,
92 map : [
93 ["0k",0x0000],
94 ["32k",0x8000],
95 ["64k",0x10000],
96 ["128k", 0x020000],
97 ["256k", 0x040000],
98 ["512k", 0x080000],
99 ],
100 defaultValue: "0k",
101 memorySection: "L2SRAM"}
102 ],
103 ];
104
105 instance:
106
107 override config string cpuCore = "6600";
108 override config string isa = "66";
109 override config string cpuCoreRevision = "1.0";
110
111 override config int minProgUnitSize = 1;
112 override config int minDataUnitSize = 1;
113 override config int dataWordSize = 4;
114
115 /*!
116 * ======== memMap ========
117 * The default memory map for this device
118 */
119 config xdc.platform.IPlatform.Memory memMap[string] = [
120 ["L2SRAM", {
121 comment: "512KB L2 SRAM/CACHE",
122 name: "L2SRAM",
123 base: 0x00800000,
124 len: 0x00080000,
125 space: "code/data",
126 access: "RWX"
127 }],
128
129 ["L1PSRAM", {
130 comment: "32KB RAM/CACHE L1 program memory",
131 name: "L1PSRAM",
132 base: 0x00E00000,
133 len: 0x00008000,
134 space: "code",
135 access: "RWX"
136 }],
137
138 ["L1DSRAM", {
139 comment: "32KB RAM/CACHE L1 data memory",
140 name: "L1DSRAM",
141 base: 0x00F00000,
142 len: 0x00008000,
143 space: "data",
144 access: "RW"
145 }],
146
147 ["MSMCSRAM", {
148 comment: "2MB MSMC SRAM",
149 name: "MSMCSRAM",
150 base: 0x0C000000,
151 len: 0x00200000,
152 space: "code/data",
153 access: "RWX"
154 }],
155 ];
156 };