1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== TMS320C6454.xdc ========
35 *
36 */
37
38 /*!
39 * ======== TMS320C6454 ========
40 * The 6454 device data sheet module.
41 *
42 * This module implements the ICpuDataSheet interface and is
43 * used by platforms to obtain "data sheet" information about this device.
44 */
45 metaonly module TMS320C6454 inherits ti.catalog.ICpuDataSheet
46 {
47 config long cacheSizeL1[string] = [
48 ["0k", 0x0000],
49 ["4k", 0x1000],
50 ["8k", 0x2000],
51 ["16k", 0x4000],
52 ["32k", 0x8000],
53 ];
54
55 config long cacheSizeL2[string] = [
56 ["0k", 0x00000],
57 ["32k", 0x08000],
58 ["64k", 0x10000],
59 ["128k", 0x20000],
60 ["256k", 0x40000]
61 ];
62
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode',{desc:"L1P Cache",
65 base: 0xE00000,
66 map : [["0k",0x0000],
67 ["4k",0x1000],
68 ["8k",0x2000],
69 ["16k",0x4000],
70 ["32k",0x8000]],
71 defaultValue: "32k",
72 memorySection: "L1PSRAM"}],
73
74 ['l1DMode',{desc:"L1D Cache",
75 base: 0xF00000,
76 map : [["0k",0x0000],
77 ["4k",0x1000],
78 ["8k",0x2000],
79 ["16k",0x4000],
80 ["32k",0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}],
83
84 ['l2Mode',{desc:"L2 Cache",
85 base: 0x800000,
86 map : [["0k",0x0000],
87 ["32k",0x8000],
88 ["64k",0x10000],
89 ["128k",0x20000],
90 ["256k",0x40000]],
91 defaultValue: "0k",
92 memorySection: "IRAM"}],
93 ];
94
95 instance:
96
97 override config string cpuCore = "64x+";
98 override config string isa = "64P";
99 override config string cpuCoreRevision = "1.0";
100
101 override config int minProgUnitSize = 1;
102 override config int minDataUnitSize = 1;
103 override config int dataWordSize = 4;
104
105 /*!
106 * ======== memMap ========
107 * The default memory map for this device
108 */
109 config xdc.platform.IPlatform.Memory memMap[string] = [
110 ["IRAM", {
111 comment: "Internal 1MB UMAP0 memory",
112 name: "IRAM",
113 base: 0x800000,
114 len: 0x100000,
115 space: "code/data",
116 access: "RWX"
117 }],
118
119 ["L1PSRAM", {
120 comment: "Internal 32KB RAM/CACHE L1 program memory",
121 name: "L1PSRAM",
122 base: 0xE00000,
123 len: 0x008000,
124 space: "code",
125 access: "RWX"
126 }],
127
128 ["L1DSRAM", {
129 comment: "Internal 32KB RAM/CACHE L1 data memory",
130 name: "L1DSRAM",
131 base: 0xF00000,
132 len: 0x008000,
133 space: "data",
134 access: "RW"
135 }],
136
137 ];
138 };