1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== TMS320C6421.xdc ========
35 *
36 */
37
38 package ti.catalog.c6000;
39
40 /*!
41 * ======== TMS320C6421 ========
42 * The C6421 device data sheet module.
43 *
44 * This module implements the xdc.platform.ICpuDataSheet interface and is
45 * used by platforms to obtain "data sheet" information about this device.
46 */
47 metaonly module TMS320C6421 inherits ti.catalog.ICpuDataSheet
48 {
49 config long cacheSizeL1[string] = [
50 ["0k", 0x0000],
51 ["4k", 0x1000],
52 ["8k", 0x2000],
53 ["16k", 0x4000],
54 ["32k", 0x4000]
55 ];
56
57 config long cacheSizeL2[string] = [
58 ["0k", 0x00000],
59 ["32k", 0x08000],
60 ["64k", 0x10000]
61 ];
62
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode',{desc:"L1P Cache",
65 base: 0x10E0C000,
66 map : [["0k",0x0000],
67 ["4k",0x1000],
68 ["8k",0x2000],
69 ["16k",0x4000],
70 ["32k",0x8000]],
71 defaultValue: "32k",
72 memorySection: "L1PSRAM"}],
73
74 ['l1DMode',{desc:"L1D Cache",
75 base: 0x10F0C000,
76 map : [["0k",0x0000],
77 ["4k",0x1000],
78 ["8k",0x2000],
79 ["16k",0x4000],
80 ["32k",0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}],
83
84 ['l2Mode',{desc:"L2 Cache",
85 base: 0x10810000,
86 map : [["0k",0x0000],
87 ["32k",0x8000],
88 ["64k",0x10000]],
89 defaultValue: "0k",
90 memorySection: "IRAM"}],
91
92 ];
93
94 instance:
95
96 override config string cpuCore = "64x+";
97 override config string isa = "64P";
98 override config string cpuCoreRevision = "1.0";
99
100 override config int minProgUnitSize = 1;
101 override config int minDataUnitSize = 1;
102 override config int dataWordSize = 4;
103
104 /*!
105 * ======== memMap ========
106 * The default memory map for this device
107 */
108 config xdc.platform.IPlatform.Memory memMap[string] = [
109 ["IRAM", {
110 comment: "Internal 64KB L2 RAM/CACHE in UMAP0 memory",
111 name: "IRAM",
112 base: 0x10810000,
113 len: 0x00010000,
114 space: "code/data",
115 access: "RWX"
116 }],
117
118 ["L1PSRAM", {
119 comment: "Internal 16KB RAM/CACHE L1 program memory",
120 name: "L1PSRAM",
121 base: 0x10E0C000,
122 len: 0x00004000,
123 space: "code",
124 access: "RWX"
125 }],
126
127 ["L1DSRAM", {
128 comment: "Internal 48KB RAM/CACHE L1 data memory",
129 name: "L1DSRAM",
130 base: 0x10F0C000,
131 len: 0x0000C000,
132 space: "data",
133 access: "RW"
134 }],
135 ];
136 };