1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*
    34     *  ======== TDA3XX.xdc ========
    35     *
    36     */
    37    
    38    package ti.catalog.c6000;
    39    
    40    /*!
    41     *  ======== TDA3XX ========
    42     *  The TDA3XX device data sheet module.
    43     *
    44     *  This module implements the ICpuDataSheet interface and is
    45     *  used by platforms to obtain "data sheet" information about this device.
    46     */
    47    metaonly module TDA3XX inherits ti.catalog.ICpuDataSheet
    48    {
    49    
    50        config long cacheSizeL1[string] = [
    51            ["0k",  0x0000],
    52            ["4k",  0x1000],
    53            ["8k",  0x2000],
    54            ["16k", 0x4000],
    55            ["32k", 0x8000]
    56        ];
    57    
    58        config long cacheSizeL2[string] = [
    59            ["0k",    0x000000],
    60            ["32k",   0x008000],
    61            ["64k",   0x010000],
    62            ["128k",  0x020000],
    63            ["256k",  0x040000]
    64        ];
    65    
    66        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    67                 ['l1PMode',{desc:"L1P Cache",
    68                             base: 0x00E00000,
    69                             map : [["0k" ,0x0000],
    70                                    ["4k" ,0x1000],
    71                                    ["8k" ,0x2000],
    72                                    ["16k",0x4000],
    73                                    ["32k",0x8000]],
    74                             defaultValue: "32k",
    75                             memorySection: "L1PSRAM"}],
    76    
    77                 ['l1DMode',{desc:"L1D Cache",
    78                             base: 0x00F00000,
    79                             map : [["0k"  ,0x0000],
    80                                    ["4k"  ,0x1000],
    81                                    ["8k"  ,0x2000],
    82                                    ["16k" ,0x4000],
    83                                    ["32k" ,0x8000]],
    84                             defaultValue: "32k",
    85                             memorySection: "L1DSRAM"}],
    86    
    87                 ['l2Mode',{desc:"L2 Cache",
    88                             base: 0x00800000,
    89                             map : [["0k"   ,0x0000],
    90                                    ["32k"  ,0x8000],
    91                                    ["64k"  ,0x10000],
    92                                ["128k" ,0x020000],
    93                                    ["256k" ,0x040000]],
    94                             defaultValue: "0k",
    95                             memorySection: "L2SRAM"}],
    96    
    97        ];
    98    
    99    instance:
   100        override config string   cpuCore         = "6600";
   101        override config string   isa             = "66";
   102        override config string   cpuCoreRevision = "1.0";
   103    
   104        override config int      minProgUnitSize = 1;
   105        override config int      minDataUnitSize = 1;
   106        override config int      dataWordSize    = 4;
   107    
   108        /*!
   109         *  ======== memMap ========
   110         *  The default memory map for this device
   111         */
   112        config xdc.platform.IPlatform.Memory memMap[string]  = [
   113            ["L2SRAM", {
   114                comment:    "288KB L2 SRAM/CACHE",
   115                name:       "L2SRAM",
   116                base:       0x00800000,
   117                len:        0x00048000,
   118                space:      "code/data",
   119                access:     "RWX"
   120            }],
   121    
   122            ["L1PSRAM", {
   123                comment:    "32KB SRAM/CACHE L1 program memory",
   124                name:       "L1PSRAM",
   125                base:       0x00E00000,
   126                len:        0x00008000,
   127                space:      "code",
   128                access:     "RWX"
   129            }],
   130    
   131            ["L1DSRAM", {
   132                comment:    "32KB SRAM/CACHE L1 data memory",
   133                name:       "L1DSRAM",
   134                base:       0x00F00000,
   135                len:        0x00008000,
   136                space:      "data",
   137                access:     "RW"
   138            }],
   139    
   140            ["OCMC_RAM", {
   141                name:       "OCMC_RAM",
   142                base:       0x40300000,
   143                len:        0x00080000
   144            }]
   145        ];
   146    };