1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== TMS320C66AK2G02.xdc ========
35 *
36 */
37
38 package ti.catalog.c6000;
39
40 metaonly module TCI66AK2G02 inherits ti.catalog.ICpuDataSheet
41 {
42 /* These are the available sizes for L1 caches */
43 config long cacheSizeL1[string] = [
44 ["0k", 0x0000],
45 ["4k", 0x1000],
46 ["8k", 0x2000],
47 ["16k", 0x4000],
48 ["32k", 0x8000],
49 ];
50
51 /* These are the available sizes for L2 cche */
52 config long cacheSizeL2[string] = [
53 ["0k", 0x000000],
54 ["32k", 0x008000],
55 ["64k", 0x010000],
56 ["128k", 0x020000],
57 ["256k", 0x040000],
58 ["512k", 0x080000],
59 ["1024k", 0x100000]
60 ];
61
62 /* This is used by platform wizard for setting default cache sizes */
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode', {
65 desc:"L1P Cache",
66 base: 0x00E00000,
67 map : [
68 ["0k", 0x0000],
69 ["4k", 0x1000],
70 ["8k", 0x2000],
71 ["16k",0x4000],
72 ["32k",0x8000]
73 ],
74 defaultValue: "32k",
75 memorySection: "L1PSRAM"
76 }],
77 ['l1DMode', {
78 desc:"L1D Cache",
79 base: 0x00F00000,
80 map : [
81 ["0k", 0x0000],
82 ["4k", 0x1000],
83 ["8k", 0x2000],
84 ["16k",0x4000],
85 ["32k",0x8000]
86 ],
87 defaultValue: "32k",
88 memorySection: "L1DSRAM"
89 }],
90 ['l2Mode', {
91 desc:"L2 Cache",
92 base: 0x00800000,
93 map : [
94 ["0k", 0x0000],
95 ["32k", 0x8000],
96 ["64k", 0x10000],
97 ["128k", 0x020000],
98 ["256k", 0x040000],
99 ["512k", 0x080000],
100 ["1024k", 0x100000]
101 ],
102 defaultValue: "0k",
103 memorySection: "L2SRAM"}
104 ],
105 ];
106
107 instance:
108
109 override config string cpuCore = "6600";
110 override config string isa = "66";
111 override config string cpuCoreRevision = "1.0";
112
113 override config int minProgUnitSize = 1;
114 override config int minDataUnitSize = 1;
115 override config int dataWordSize = 4;
116
117 /*!
118 * ======== memMap ========
119 * The default memory map for this device
120 */
121 config xdc.platform.IPlatform.Memory memMap[string] = [
122 ["L2SRAM", {
123 comment: "1MB L2 SRAM/CACHE",
124 name: "L2SRAM",
125 base: 0x00800000,
126 len: 0x00100000,
127 space: "code/data",
128 access: "RWX"
129 }],
130
131 ["L1PSRAM", {
132 comment: "32KB RAM/CACHE L1 program memory",
133 name: "L1PSRAM",
134 base: 0x00E00000,
135 len: 0x00008000,
136 space: "code",
137 access: "RWX"
138 }],
139
140 ["L1DSRAM", {
141 comment: "32KB RAM/CACHE L1 data memory",
142 name: "L1DSRAM",
143 base: 0x00F00000,
144 len: 0x00008000,
145 space: "data",
146 access: "RW"
147 }],
148
149 ["MSMCSRAM", {
150 comment: "1MB MSMC SRAM",
151 name: "MSMCSRAM",
152 base: 0x0C000000,
153 len: 0x00100000,
154 space: "code/data",
155 access: "RWX"
156 }],
157 ];
158 };