1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== Kepler.xdc ========
35 *
36 */
37
38 package ti.catalog.c6000;
39
40 metaonly module Kepler inherits ti.catalog.ICpuDataSheet
41 {
42
43 config long cacheSizeL1[string] = [
44 ["0k", 0x0000],
45 ["4k", 0x1000],
46 ["8k", 0x2000],
47 ["16k", 0x4000],
48 ["32k", 0x8000],
49 ];
50
51 config long cacheSizeL2[string] = [
52 ["0k", 0x000000],
53 ["32k", 0x008000],
54 ["64k", 0x010000],
55 ["128k", 0x020000],
56 ["256k", 0x040000],
57 ["512k", 0x080000],
58 ["1024k", 0x100000]
59 ];
60
61 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
62 ['l1PMode',
63 {desc:"L1P Cache",
64 base: 0x00E00000,
65 map : [["0k",0x0000],
66 ["4k",0x1000],
67 ["8k",0x2000],
68 ["16k",0x4000],
69 ["32k",0x8000]],
70 defaultValue: "32k",
71 memorySection: "L1PSRAM"
72 }
73 ],
74 ['l1DMode',
75 {desc:"L1D Cache",
76 base: 0x00F00000,
77 map : [["0k",0x0000],
78 ["4k",0x1000],
79 ["8k",0x2000],
80 ["16k",0x4000],
81 ["32k",0x8000]],
82 defaultValue: "32k",
83 memorySection: "L1DSRAM"
84 }
85 ],
86 ['l2Mode',
87 {desc:"L2 Cache",
88 base: 0x00800000,
89 map : [["0k",0x0000],
90 ["32k",0x8000],
91 ["64k",0x10000],
92 ["128k", 0x020000],
93 ["256k", 0x040000],
94 ["512k", 0x080000],
95 ["1024k", 0x100000]],
96 defaultValue: "0k",
97 memorySection: "L2SRAM"
98 }
99 ],
100 ];
101
102 instance:
103
104 override config string cpuCore = "6600";
105 override config string isa = "66";
106 override config string cpuCoreRevision = "1.0";
107
108 override config int minProgUnitSize = 1;
109 override config int minDataUnitSize = 1;
110 override config int dataWordSize = 4;
111
112 /*!
113 * ======== memMap ========
114 * The default memory map for this device
115 */
116 config xdc.platform.IPlatform.Memory memMap[string] = [
117 ["L2SRAM", {
118 comment: "1MB L2 SRAM/CACHE",
119 name: "L2SRAM",
120 base: 0x00800000,
121 len: 0x00100000,
122 space: "code/data",
123 access: "RWX"
124 }],
125
126 ["L1PSRAM", {
127 comment: "32KB RAM/CACHE L1 program memory",
128 name: "L1PSRAM",
129 base: 0x00E00000,
130 len: 0x00008000,
131 space: "code",
132 access: "RWX"
133 }],
134
135 ["L1DSRAM", {
136 comment: "32KB RAM/CACHE L1 data memory",
137 name: "L1DSRAM",
138 base: 0x00F00000,
139 len: 0x00008000,
140 space: "data",
141 access: "RW"
142 }],
143
144 ["MSMCSRAM", {
145 comment: "6MB MSMC SRAM",
146 name: "MSMCSRAM",
147 base: 0x0C000000,
148 len: 0x00600000,
149 space: "code/data",
150 access: "RWX"
151 }],
152 ];
153 };