1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== ITMS320TCI6616.xdc ========
35 *
36 */
37
38 package ti.catalog.c6000;
39
40 metaonly interface ITMS320TCI6616 inherits ti.catalog.ICpuDataSheet
41 {
42
43 config long cacheSizeL1[string] = [
44 ["0k", 0x0000],
45 ["4k", 0x1000],
46 ["8k", 0x2000],
47 ["16k", 0x4000],
48 ["32k", 0x8000],
49 ];
50
51 config long cacheSizeL2[string] = [
52 ["0k", 0x000000],
53 ["32k", 0x008000],
54 ["64k", 0x010000],
55 ["128k", 0x020000],
56 ["256k", 0x040000],
57 ["512k", 0x080000],
58 ["1024k", 0x100000]
59 ];
60
61 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
62 ['l1PMode',{desc:"L1P Cache",
63 base: 0x00E00000,
64 map : [["0k",0x0000],
65 ["4k",0x1000],
66 ["8k",0x2000],
67 ["16k",0x4000],
68 ["32k",0x8000]],
69 defaultValue: "32k",
70 memorySection: "L1PSRAM"}],
71
72 ['l1DMode',{desc:"L1D Cache",
73 base: 0x00F00000,
74 map : [["0k",0x0000],
75 ["4k",0x1000],
76 ["8k",0x2000],
77 ["16k",0x4000],
78 ["32k",0x8000]],
79 defaultValue: "32k",
80 memorySection: "L1DSRAM"}],
81
82 ['l2Mode',{desc:"L2 Cache",
83 base: 0x00800000,
84 map : [["0k",0x0000],
85 ["32k",0x8000],
86 ["64k",0x10000],
87 ["128k", 0x020000],
88 ["256k", 0x040000],
89 ["512k", 0x080000],
90 ["1024k", 0x100000]],
91 defaultValue: "0k",
92 memorySection: "L2SRAM"}],
93
94 ];
95
96 instance:
97
98 override config string cpuCore = "6600";
99 override config string isa = "66";
100 override config string cpuCoreRevision = "1.0";
101
102 override config int minProgUnitSize = 1;
103 override config int minDataUnitSize = 1;
104 override config int dataWordSize = 4;
105
106 /*!
107 * ======== memMap ========
108 * The default memory map for this device
109 */
110 config xdc.platform.IPlatform.Memory memMap[string] = [
111 ["L2SRAM", {
112 comment: "1MB L2 SRAM/CACHE",
113 name: "L2SRAM",
114 base: 0x00800000,
115 len: 0x00100000,
116 space: "code/data",
117 access: "RWX"
118 }],
119
120 ["L1PSRAM", {
121 comment: "32KB RAM/CACHE L1 program memory",
122 name: "L1PSRAM",
123 base: 0x00E00000,
124 len: 0x00008000,
125 space: "code",
126 access: "RWX"
127 }],
128
129 ["L1DSRAM", {
130 comment: "32KB RAM/CACHE L1 data memory",
131 name: "L1DSRAM",
132 base: 0x00F00000,
133 len: 0x00008000,
134 space: "data",
135 access: "RW"
136 }],
137
138 ["MSMCSRAM", {
139 comment: "2MB MSMC SRAM",
140 name: "MSMCSRAM",
141 base: 0x0C000000,
142 len: 0x00200000,
143 space: "code/data",
144 access: "RWX"
145 }],
146 ];
147 };