1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== ITMS320DA8xx.xdc ========
35 *
36 */
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== ITMS320DA8xx ========
41 * An interface implemented by TMS320DA8xx devices.
42 *
43 */
44 metaonly interface ITMS320DA8xx inherits ti.catalog.ICpuDataSheet
45 {
46
47 config long cacheSizeL1[string] = [
48 ["0k", 0x0000],
49 ["4k", 0x1000],
50 ["8k", 0x2000],
51 ["16k", 0x4000],
52 ["32k", 0x8000],
53 ];
54
55 config long cacheSizeL2[string] = [
56 ["0k", 0x00000],
57 ["32k", 0x08000],
58 ["64k", 0x10000],
59 ["128k",0x20000],
60 ["256k",0x40000],
61 ];
62
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode',{desc:"L1P Cache",
65 base: 0x11E00000,
66 map : [["0k",0x0000],
67 ["4k",0x1000],
68 ["8k",0x2000],
69 ["16k",0x4000],
70 ["32k",0x8000]],
71 defaultValue: "32k",
72 memorySection: "L1PSRAM"}],
73
74 ['l1DMode',{desc:"L1D Cache",
75 base: 0x11F00000,
76 map : [["0k",0x0000],
77 ["4k",0x1000],
78 ["8k",0x2000],
79 ["16k",0x4000],
80 ["32k",0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}],
83
84 ['l2Mode',{desc:"L2 Cache",
85 base: 0x11800000,
86 map : [["0k",0x0000],
87 ["32k",0x8000],
88 ["64k",0x10000],
89 ["128k",0x20000],
90 ["256k",0x40000]],
91 defaultValue: "0k",
92 memorySection: "IRAM"}],
93
94 ];
95
96 instance:
97 override config int minProgUnitSize = 1;
98 override config int minDataUnitSize = 1;
99 override config int dataWordSize = 4;
100
101 override config string cpuCore = "C674";
102 override config string isa = "674";
103 override config string cpuCoreRevision = "1.0";
104
105 config xdc.platform.IPlatform.Memory memMap[string] = [
106 ["IROM", {
107 comment: "Internal 1MB L2 ROM",
108 name: "IROM",
109 base: 0x11700000,
110 len: 0x00100000,
111 space: "code/data",
112 access: "RX"
113 }],
114
115 ["IRAM", {
116 comment: "Internal 256KB L2 memory",
117 name: "IRAM",
118 base: 0x11800000,
119 len: 0x00040000,
120 space: "code/data",
121 access: "RWX"
122 }],
123
124 ["L1PSRAM", {
125 comment: "Internal 32KB L1 program memory",
126 name: "L1PSRAM",
127 base: 0x11E00000,
128 len: 0x00008000,
129 space: "code",
130 access: "RWX"
131 }],
132
133 ["L1DSRAM", {
134 comment: "Internal 32KB L1 data memory",
135 name: "L1DSRAM",
136 base: 0x11F00000,
137 len: 0x00008000,
138 space: "data",
139 access: "RW"
140 }],
141
142 ["L3_CBA_RAM", {
143 comment: "128KB ARM/DSP local shared RAM",
144 name: "L3_CBA_RAM",
145 base: 0x80000000,
146 len: 0x00020000,
147 space: "code/data",
148 access: "RWX"
149 }],
150 ];
151 };