1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
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10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
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17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== ITMS320CTCI648x.xdc ========
35 *
36 */
37
38 /*!
39 * ======== ITMS320CTCI648x ========
40 * An interface implemented by TCI6487 and TCI6488 devices
41 *
42 * This interface is defined to factor common data about TCI6487 and TCI6488
43 * devices into a single place; they are all the same from the configuration
44 * point of view.
45 */
46 metaonly interface ITMS320CTCI648x inherits ti.catalog.ICpuDataSheet
47 {
48
49 config long cacheSizeL1[string] = [
50 ["0k", 0x0000],
51 ["4k", 0x1000],
52 ["8k", 0x2000],
53 ["16k", 0x4000],
54 ["32k", 0x8000],
55 ];
56
57 config long cacheSizeL2[string] = [
58 ["0k", 0x00000],
59 ["32k", 0x08000],
60 ["64k", 0x10000],
61 ["128k", 0x20000],
62 ["256k", 0x40000]
63 ];
64
65 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
66 ['l1PMode',{desc:"L1P Cache",
67 base: 0xE00000,
68 map : [["0k",0x0000],
69 ["4k",0x1000],
70 ["8k",0x2000],
71 ["16k",0x4000],
72 ["32k",0x8000]],
73 defaultValue: "32k",
74 memorySection: "L1PSRAM"}],
75
76 ['l1DMode',{desc:"L1D Cache",
77 base: 0xF00000,
78 map : [["0k",0x0000],
79 ["4k",0x1000],
80 ["8k",0x2000],
81 ["16k",0x4000],
82 ["32k",0x8000]],
83 defaultValue: "32k",
84 memorySection: "L1DSRAM"}],
85
86 ['l2Mode',{desc:"L2 Cache",
87 base: 0x00800000,
88 map : [["0k",0x0000],
89 ["32k",0x8000],
90 ["64k",0x10000],
91 ["128k",0x20000],
92 ["256k",0x40000]],
93 defaultValue: "0k",
94 memorySection: "L2RAM"}]
95
96 ];
97
98 config xdc.platform.IPlatform.Memory memBlock[string] = [
99 ["ASYMGEM0L2RAM", {
100 comment: "1536K L2 RAM/CACHE memory",
101 name: "L2RAM",
102 base: 0x00800000,
103 len: 0x00180000,
104 space: "code/data",
105 access: "RWX"
106 }],
107
108 ["ASYMGEM1L2RAM", {
109 comment: "1024K L2 RAM/CACHE memory",
110 name: "L2RAM",
111 base: 0x00800000,
112 len: 0x00100000,
113 space: "code/data",
114 access: "RWX"
115 }],
116
117 ["ASYMGEM2L2RAM", {
118 comment: "512K L2 RAM/CACHE memory",
119 name: "L2RAM",
120 base: 0x00800000,
121 len: 0x00080000,
122 space: "code/data",
123 access: "RWX"
124 }],
125
126 ["SYMGEML2RAM", {
127 comment: "1024K L2 RAM/CACHE memory",
128 name: "L2RAM",
129 base: 0x00800000,
130 len: 0x00100000,
131 space: "code/data",
132 access: "RWX"
133 }],
134
135 ];
136
137 instance:
138
139 override config string cpuCore = "64x+";
140 override config string isa = "64P";
141 override config string cpuCoreRevision = "1.0";
142
143 override config int minProgUnitSize = 1;
144 override config int minDataUnitSize = 1;
145 override config int dataWordSize = 4;
146
147 /*!
148 * ======== memMap ========
149 * The default memory map for this device
150 */
151 config xdc.platform.IPlatform.Memory memMap[string] = [
152
153 ["L1PSRAM", {
154 comment: "Internal 32KB RAM/CACHE L1 program memory",
155 name: "L1PSRAM",
156 base: 0xE00000,
157 len: 0x008000,
158 space: "code",
159 access: "RWX"
160 }],
161
162 ["L1DSRAM", {
163 comment: "Internal 32KB RAM/CACHE L1 data memory",
164 name: "L1DSRAM",
165 base: 0xF00000,
166 len: 0x008000,
167 space: "data",
168 access: "RW"
169 }],
170 ];
171
172 };