1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== ITMS320CTCI6484.xdc ========
35 *
36 */
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== ITMS320CTCI6484 ========
41 */
42 metaonly interface ITMS320CTCI6484 inherits ti.catalog.ICpuDataSheet
43 {
44
45 config long cacheSizeL1[string] = [
46 ["0k", 0x0000],
47 ["4k", 0x1000],
48 ["8k", 0x2000],
49 ["16k", 0x4000],
50 ["32k", 0x8000],
51 ];
52
53 config long cacheSizeL2[string] = [
54 ["0k", 0x000000],
55 ["32k", 0x008000],
56 ["64k", 0x010000],
57 ["128k", 0x020000],
58 ["256k", 0x040000],
59 ["512k", 0x080000],
60 ["1024k", 0x100000]
61 ];
62
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode',{desc:"L1P Cache",
65 base: 0xE00000,
66 map : [["0k",0x0000],
67 ["4k",0x1000],
68 ["8k",0x2000],
69 ["16k",0x4000],
70 ["32k",0x8000]],
71 defaultValue: "32k",
72 memorySection: "L1PSRAM"}],
73
74 ['l1DMode',{desc:"L1D Cache",
75 base:0xF00000,
76 map : [["0k",0x0000],
77 ["4k",0x1000],
78 ["8k",0x2000],
79 ["16k",0x4000],
80 ["32k",0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}],
83
84 ['l2Mode',{desc:"L2 Cache",
85 base:0x800000,
86 map : [["0k",0x0000],
87 ["32k",0x8000],
88 ["64k",0x10000],
89 ["128k",0x20000],
90 ["256k",0x40000],
91 ["512k", 0x080000],
92 ["1024k", 0x100000]],
93 defaultValue: "0k",
94 memorySection: "IRAM"}],
95
96 ];
97
98 instance:
99
100 override config string cpuCore = "64x+";
101 override config string isa = "64P";
102 override config string cpuCoreRevision = "1.0";
103
104 override config int minProgUnitSize = 1;
105 override config int minDataUnitSize = 1;
106 override config int dataWordSize = 4;
107
108 /*!
109 * ======== memMap ========
110 * The default memory map for this device
111 */
112 config xdc.platform.IPlatform.Memory memMap[string] = [
113 ["IRAM", {
114 comment: "Internal 2MB L2 memory",
115 name: "IRAM",
116 base: 0x800000,
117 len: 0x200000,
118 space: "code/data",
119 access: "RWX"
120 }],
121
122 ["L1PSRAM", {
123 comment: "Internal 32KB RAM/CACHE L1 program memory",
124 name: "L1PSRAM",
125 base: 0xE00000,
126 len: 0x008000,
127 space: "code",
128 access: "RWX"
129 }],
130
131 ["L1DSRAM", {
132 comment: "Internal 32KB RAM/CACHE L1 data memory",
133 name: "L1DSRAM",
134 base: 0xF00000,
135 len: 0x008000,
136 space: "data",
137 access: "RW"
138 }],
139
140 ];
141 };