1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== ITMS320CDRx40x.xdc ========
35 *
36 */
37
38 /*!
39 * ======== ITMS320CDRx40x ========
40 * An interface implemented by all DRx40x and DRx41x devices
41 *
42 * This interface is defined to factor common data about all DRA40x and
43 * DRA41x devices into a single file; they are all configured in the same way.
44 */
45 metaonly interface ITMS320CDRx40x inherits ti.catalog.ICpuDataSheet
46 {
47 config long cacheSizeL1[string] = [
48 ["0k", 0x0000],
49 ["4k", 0x1000],
50 ["8k", 0x2000],
51 ["16k", 0x4000],
52 ["32k", 0x8000],
53 ];
54
55 config long cacheSizeL2[string] = [
56 ["0k", 0x00000],
57 ["32k", 0x08000],
58 ["64k", 0x10000],
59 ["128k",0x20000],
60 ];
61
62 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
63 ['l1PMode',{desc:"L1P Cache",
64 base:0x11E00000,
65 map : [["0k",0x0000],
66 ["4k",0x1000],
67 ["8k",0x2000],
68 ["16k",0x4000]],
69 defaultValue: "16k",
70 memorySection: "L1PSRAM"}],
71
72 ['l1DMode',{desc:"L1D Cache",
73 base:0x11F00000,
74 map : [["0k",0x0000],
75 ["4k",0x1000],
76 ["8k",0x2000],
77 ["16k",0x4000],
78 ["32k",0x8000]],
79 defaultValue: "32k",
80 memorySection: "L1DSRAM"}],
81
82 ['l2Mode',{desc:"L2 Cache",
83 base: 0x11810000,
84 map : [["0k",0x0000],
85 ["32k",0x8000],
86 ["64k",0x10000],
87 ["128k",0x20000]],
88 defaultValue: "0k",
89 memorySection: "IRAM"}]
90
91 ];
92
93 instance:
94
95 override config string cpuCore = "64x+";
96 override config string isa = "64P";
97 override config string cpuCoreRevision = "1.0";
98
99 override config int minProgUnitSize = 1;
100 override config int minDataUnitSize = 1;
101 override config int dataWordSize = 4;
102
103 /*!
104 * ======== memMap ========
105 * The default memory map for this device
106 */
107 config xdc.platform.IPlatform.Memory memMap[string] = [
108 ["IRAM", {
109 comment: "Internal 192KB UMAP0 memory",
110 name: "IRAM",
111 base: 0x11810000,
112 len: 0x00030000,
113 space: "code/data",
114 access: "RWX"
115 }],
116
117 ["L1PSRAM", {
118 comment: "Internal 16KB RAM/CACHE L1 program memory",
119 name: "L1PSRAM",
120 base: 0x11E00000,
121 len: 0x00004000,
122 space: "code",
123 access: "RWX"
124 }],
125
126 ["L1DSRAM", {
127 comment: "Internal 32KB RAM/CACHE L1 data memory",
128 name: "L1DSRAM",
129 base: 0x11F00000,
130 len: 0x00008000,
131 space: "data",
132 access: "RW"
133 }],
134
135 ["ARM_RAM", {
136 comment: "Internal ARM RAM memory",
137 name: "ARM_RAM",
138 base: 0x10008000,
139 len: 0x00004000,
140 space: "data",
141 access: "RW"
142 }],
143 ];
144 };