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37
38 /*!
39 * ======== ITMS320CDRA45x ========
40 * An interface implemented by all DRA45x devices
41 *
42 * This interface is defined to factor common data about all DRA45x devices
43 * into a single place; they are all the same from the configuration point of
44 * view.
45 */
46 metaonly interface ITMS320CDRA45x inherits ti.catalog.ICpuDataSheet
47 {
48 config long cacheSizeL1[string] = [
49 ["0k", 0x0000],
50 ["4k", 0x1000],
51 ["8k", 0x2000],
52 ["16k", 0x4000],
53 ["32k", 0x8000],
54 ];
55
56 config long cacheSizeL2[string] = [
57 ["0k", 0x00000],
58 ["32k", 0x08000],
59 ["64k", 0x10000],
60 ["128k", 0x20000]
61 ];
62
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode',{desc:"L1P Cache",
65 base:0x11E08000,
66 map : [["0k",0x0000],
67 ["4k",0x1000],
68 ["8k",0x2000],
69 ["16k",0x4000],
70 ["32k",0x8000]],
71 defaultValue: "32k",
72 memorySection: "L1PSRAM"}],
73
74 ['l1DMode',{desc:"L1D Cache",
75 base:0x11F04000,
76 map : [["0k",0x0000],
77 ["4k",0x1000],
78 ["8k",0x2000],
79 ["16k",0x4000],
80 ["32k",0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}],
83
84 ['l2Mode',{desc:"L2 Cache",
85 base:0x11800000,
86 map : [["0k",0x0000],
87 ["32k",0x8000],
88 ["64k",0x10000],
89 ["128k",0x20000]],
90 defaultValue: "0k",
91 memorySection: "IRAM"}],
92
93 ];
94
95 instance:
96
97 override config string cpuCore = "64x+";
98 override config string isa = "64P";
99 override config string cpuCoreRevision = "1.0";
100
101 override config int minProgUnitSize = 1;
102 override config int minDataUnitSize = 1;
103 override config int dataWordSize = 4;
104
105 /*!
106 * ======== memMap ========
107 * The default memory map for this device
108 */
109 config xdc.platform.IPlatform.Memory memMap[string] = [
110 ["IRAM", {
111 comment: "Internal 128KB UMAP0 memory",
112 name: "IRAM",
113 base: 0x11800000,
114 len: 0x00020000,
115 space: "code/data",
116 access: "RWX"
117 }],
118
119 ["L1PSRAM", {
120 comment: "Internal 32KB RAM/CACHE L1 program memory",
121 name: "L1PSRAM",
122 base: 0x11E08000,
123 len: 0x00008000,
124 space: "code",
125 access: "RWX"
126 }],
127
128 ["L1DSRAM", {
129 comment: "Internal 80KB RAM/CACHE L1 data memory",
130 name: "L1DSRAM",
131 base: 0x11F04000,
132 len: 0x00014000,
133 space: "data",
134 access: "RW"
135 }],
136
137 ["ARM_RAM", {
138 comment: "Internal ARM RAM memory",
139 name: "ARM_RAM",
140 base: 0x10008000,
141 len: 0x00004000,
142 space: "data",
143 access: "RW"
144 }],
145 ];
146 };