1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== ITMS320CDM6467.xdc ========
35 *
36 */
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== ITMS320CDM6467 ========
41 * An interface implemented by all DaVinci-HD devices
42 *
43 * This interface is defined to factor common data about all DaVinci-HD devices
44 * into a single place; they are all the same from the configuration point of
45 * view.
46 */
47 metaonly interface ITMS320CDM6467 inherits ti.catalog.ICpuDataSheet
48 {
49 config long cacheSizeL1[string] = [
50 ["0k", 0x0000],
51 ["4k", 0x1000],
52 ["8k", 0x2000],
53 ["16k", 0x4000],
54 ["32k", 0x8000],
55 ];
56
57 config long cacheSizeL2[string] = [
58 ["0k", 0x00000],
59 ["32k", 0x08000],
60 ["64k", 0x10000],
61 ["128k", 0x20000],
62 ];
63
64 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
65 ['l1PMode',{desc:"L1P Cache",
66 base:0x11E00000,
67 map : [["0k",0x0000],
68 ["4k",0x1000],
69 ["8k",0x2000],
70 ["16k",0x4000],
71 ["32k",0x8000]],
72 defaultValue: "32k",
73 memorySection: "L1PSRAM"}],
74
75 ['l1DMode',{desc:"L1D Cache",
76 base: 0x11F00000,
77 map : [["0k",0x0000],
78 ["4k",0x1000],
79 ["8k",0x2000],
80 ["16k",0x4000],
81 ["32k",0x8000]],
82 defaultValue: "32k",
83 memorySection: "L1DSRAM"}],
84
85 ['l2Mode',{desc:"L2 Cache",
86 base:0x11818000,
87 map : [["0k",0x0000],
88 ["32k",0x8000],
89 ["64k",0x10000],
90 ["128k",0x20000]],
91 defaultValue: "0k",
92 memorySection: "IRAM"}]
93
94 ];
95
96 instance:
97
98 override config string cpuCore = "64x+";
99 override config string isa = "64P";
100 override config string cpuCoreRevision = "1.0";
101
102 override config int minProgUnitSize = 1;
103 override config int minDataUnitSize = 1;
104 override config int dataWordSize = 4;
105
106 /*!
107 * ======== memMap ========
108 * The default memory map for this device
109 */
110 config xdc.platform.IPlatform.Memory memMap[string] = [
111 ["ARM_RAM", {
112 comment: "Internal ARM RAM memory",
113 name: "ARM_RAM",
114 base: 0x10010000,
115 len: 0x00008000,
116 space: "data",
117 access: "RW"
118 }],
119
120 ["IRAM", {
121 comment: "Internal 128KB UMAP0 memory",
122 name: "IRAM",
123 base: 0x11818000,
124 len: 0x00020000,
125 space: "code/data",
126 access: "RWX"
127 }],
128
129 ["L1PSRAM", {
130 comment: "Internal 32KB RAM/CACHE L1 program memory",
131 name: "L1PSRAM",
132 base: 0x11E00000,
133 len: 0x00008000,
134 space: "code",
135 access: "RWX"
136 }],
137
138 ["L1DSRAM", {
139 comment: "Internal 32KB RAM/CACHE L1 data memory",
140 name: "L1DSRAM",
141 base: 0x11F00000,
142 len: 0x00008000,
143 space: "data",
144 access: "RW"
145 }],
146 ];
147 };