1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== ITMS320C6452.xdc ========
35 *
36 */
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== ITMS320C6452 ========
41 * The interface for 6452 and similar devices' data sheet module.
42 *
43 * This module implements the ICpuDataSheet interface and is
44 * used by platforms to obtain "data sheet" information about this device.
45 */
46 metaonly interface ITMS320C6452 inherits ti.catalog.ICpuDataSheet
47 {
48
49 config long cacheSizeL1[string] = [
50 ["0k", 0x0000],
51 ["4k", 0x1000],
52 ["8k", 0x2000],
53 ["16k", 0x4000],
54 ["32k", 0x8000],
55 ];
56
57 config long cacheSizeL2[string] = [
58 ["0k", 0x00000],
59 ["32k", 0x08000],
60 ["64k", 0x10000],
61 ["128k", 0x20000],
62 ["256k", 0x40000]
63 ];
64
65 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
66 ['l1PMode',{desc:"L1P Cache",
67 base:0xE00000,
68 map : [["0k",0x0000],
69 ["4k",0x1000],
70 ["8k",0x2000],
71 ["16k",0x4000],
72 ["32k",0x8000]],
73 defaultValue: "32k",
74 memorySection: "L1PSRAM"}],
75
76 ['l1DMode',{desc:"L1D Cache",
77 base:0xF00000,
78 map : [["0k",0x0000],
79 ["4k",0x1000],
80 ["8k",0x2000],
81 ["16k",0x4000],
82 ["32k",0x8000]],
83 defaultValue: "32k",
84 memorySection: "L1DSRAM"}],
85
86 ['l2Mode',{desc:"L2 Cache",
87 base:0xA00000,
88 map : [["0k",0x0000],
89 ["32k",0x8000],
90 ["64k",0x10000],
91 ["128k",0x20000],
92 ["256k",0x40000]],
93 defaultValue: "0k",
94 memorySection: "IRAM"}],
95 ];
96
97 instance:
98
99 override config string cpuCore = "64x+";
100 override config string isa = "64P";
101 override config string cpuCoreRevision = "1.0";
102
103 override config int minProgUnitSize = 1;
104 override config int minDataUnitSize = 1;
105 override config int dataWordSize = 4;
106
107 /*!
108 * ======== memMap ========
109 * The default memory map for this device
110 */
111 config xdc.platform.IPlatform.Memory memMap[string] = [
112 ["IRAM", {
113 comment: "Internal 1408KB L2 RAM/CACHE",
114 name: "IRAM",
115 base: 0xA00000,
116 len: 0x160000,
117 space: "code/data",
118 access: "RWX"
119 }],
120
121 ["L1PSRAM", {
122 comment: "Internal 32KB RAM/CACHE L1 program memory",
123 name: "L1PSRAM",
124 base: 0xE00000,
125 len: 0x008000,
126 space: "code",
127 access: "RWX"
128 }],
129
130 ["L1DSRAM", {
131 comment: "Internal 32KB RAM/CACHE L1 data memory",
132 name: "L1DSRAM",
133 base: 0xF00000,
134 len: 0x008000,
135 space: "data",
136 access: "RW"
137 }],
138
139 ];
140 };