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37
38 /*!
39 * ======== ITMS320C642x ========
40 * The C642x device data sheet module.
41 *
42 * This module implements the ICpuDataSheet interface and is
43 * used by platforms to obtain "data sheet" information about this device.
44 */
45 metaonly interface ITMS320C642x inherits ti.catalog.ICpuDataSheet
46 {
47 config long cacheSizeL1[string] = [
48 ["0k", 0x0000],
49 ["4k", 0x1000],
50 ["8k", 0x2000],
51 ["16k", 0x4000],
52 ["32k", 0x8000],
53 ];
54
55 config long cacheSizeL2[string] = [
56 ["0k", 0x00000],
57 ["32k", 0x08000],
58 ["64k", 0x10000],
59 ["128k", 0x20000]
60 ];
61
62 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
63 ['l1PMode',{desc:"L1P Cache",
64 base:0x10E08000,
65 map : [["0k",0x0000],
66 ["4k",0x1000],
67 ["8k",0x2000],
68 ["16k",0x4000],
69 ["32k",0x8000]],
70 defaultValue: "32k",
71 memorySection: "L1PSRAM"}],
72
73 ['l1DMode',{desc:"L1D Cache",
74 base:0x10F04000,
75 map : [["0k",0x0000],
76 ["4k",0x1000],
77 ["8k",0x2000],
78 ["16k",0x4000],
79 ["32k",0x8000]],
80 defaultValue: "32k",
81 memorySection: "L1DSRAM"}],
82
83 ['l2Mode',{desc:"L2 Cache",
84 base:0x10800000,
85 map : [["0k",0x0000],
86 ["32k",0x8000],
87 ["64k",0x10000],
88 ["128k",0x20000]],
89 defaultValue: "0k",
90 memorySection: "IRAM"}],
91
92 ];
93
94 instance:
95
96 override config string cpuCore = "64x+";
97 override config string isa = "64P";
98 override config string cpuCoreRevision = "1.0";
99
100 override config int minProgUnitSize = 1;
101 override config int minDataUnitSize = 1;
102 override config int dataWordSize = 4;
103
104 /*!
105 * ======== memMap ========
106 * The default memory map for this device
107 */
108 config xdc.platform.IPlatform.Memory memMap[string] = [
109 ["IRAM", {
110 comment: "Internal 128KB UMAP0 memory",
111 name: "IRAM",
112 base: 0x10800000,
113 len: 0x00020000,
114 space: "code/data",
115 access: "RWX"
116 }],
117
118 ["L1PSRAM", {
119 comment: "Internal 32KB RAM/CACHE L1 program memory",
120 name: "L1PSRAM",
121 base: 0x10E08000,
122 len: 0x00008000,
123 space: "code",
124 access: "RWX"
125 }],
126
127 ["L1DSRAM", {
128 comment: "Internal 80KB RAM/CACHE L1 data memory",
129 name: "L1DSRAM",
130 base: 0x10F04000,
131 len: 0x00014000,
132 space: "data",
133 access: "RW"
134 }],
135 ];
136 };