1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== ITI8168.xdc ========
35 *
36 */
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== ITI8168 ========
41 * An interface implemented by all TI8168 devices
42 *
43 * This interface is defined to factor common data about all TI8168 type devices
44 * into a single place; they all have the same internal memory.
45 */
46 metaonly interface ITI8168 inherits ti.catalog.ICpuDataSheet
47 {
48
49 config long cacheSizeL1[string] = [
50 ["0k", 0x0000],
51 ["4k", 0x1000],
52 ["8k", 0x2000],
53 ["16k", 0x4000],
54 ["32k", 0x8000],
55 ];
56
57 config long cacheSizeL2[string] = [
58 ["0k", 0x00000],
59 ["32k", 0x08000],
60 ["64k", 0x10000],
61 ["128k", 0x20000],
62 ["256k", 0x40000],
63 ];
64
65 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
66 ['l1PMode', {desc: "L1P Cache",
67 base: 0x10E00000,
68 map : [["0k", 0x0000],
69 ["4k", 0x1000],
70 ["8k", 0x2000],
71 ["16k", 0x4000],
72 ["32k", 0x8000]],
73 defaultValue: "32k",
74 memorySection: "L1PSRAM"}],
75
76 ['l1DMode', {desc: "L1D Cache",
77 base: 0x10F00000,
78 map : [["0k", 0x0000],
79 ["4k", 0x1000],
80 ["8k", 0x2000],
81 ["16k", 0x4000],
82 ["32k", 0x8000]],
83 defaultValue: "32k",
84 memorySection: "L1DSRAM"}],
85
86 ['l2Mode', {desc: "L2 Cache",
87 base: 0x10800000,
88 map : [["0k", 0x00000],
89 ["32k", 0x08000],
90 ["64k", 0x10000],
91 ["128k", 0x20000],
92 ["256k", 0x40000]],
93 defaultValue: "0k",
94 memorySection: "IRAM"}],
95
96 ];
97
98 instance:
99 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
100 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp1;
101 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp2;
102
103 override config int minProgUnitSize = 1;
104 override config int minDataUnitSize = 1;
105 override config int dataWordSize = 4;
106
107 override config string cpuCore = "674";
108 override config string isa = "674";
109 override config string cpuCoreRevision = "1.0";
110
111 config xdc.platform.IPlatform.Memory memMap[string] = [
112
113 ["IRAM", {
114 comment: "Internal 256KB L2 memory",
115 name: "IRAM",
116 base: 0x10800000,
117 len: 0x40000,
118 space: "code/data",
119 access: "RWX"
120 }],
121
122 ["L1PSRAM", {
123 comment: "Internal 32KB L1 program memory",
124 name: "L1PSRAM",
125 base: 0x10E00000,
126 len: 0x8000,
127 space: "code",
128 access: "RWX"
129 }],
130
131 ["L1DSRAM", {
132 comment: "Internal 32KB L1 data memory",
133 name: "L1DSRAM",
134 base: 0x10F00000,
135 len: 0x8000,
136 space: "data",
137 access: "RW"
138 }],
139
140 ["OCMC_0", {
141 comment: "OCMC (On-chip RAM) Bank 0 (256KB)",
142 name: "OCMC_0",
143 base: 0x40300000,
144 len: 0x40000,
145 space: "code/data",
146 access: "RWX"
147 }],
148
149 ["OCMC_1", {
150 comment: "OCMC (On-chip RAM) Bank 1 (256KB)",
151 name: "OCMC_1",
152 base: 0x40400000,
153 len: 0x40000,
154 space: "code/data",
155 access: "RWX"
156 }],
157 ];
158 };