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32
33 34 35 36
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== ITI811X ========
41 * An interface implemented by all TI811X devices
42 *
43 * This interface is defined to factor common data about all TI811X type
44 * devices into a single place; they all have the same internal memory.
45 */
46 metaonly interface ITI811X inherits ti.catalog.ICpuDataSheet
47 {
48 config long cacheSizeL1[string] = [
49 ["0k", 0x0000],
50 ["4k", 0x1000],
51 ["8k", 0x2000],
52 ["16k", 0x4000],
53 ["32k", 0x8000],
54 ];
55
56 config long cacheSizeL2[string] = [
57 ["0k", 0x00000],
58 ["32k", 0x08000],
59 ["64k", 0x10000],
60 ["128k",0x20000],
61 ["256k",0x40000],
62 ];
63
64 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
65 ['l1PMode',{desc:"L1P Cache",
66 base:0x10E00000,
67 map : [["0k",0x0000],
68 ["4k",0x1000],
69 ["8k",0x2000],
70 ["16k",0x4000],
71 ["32k",0x8000]],
72 defaultValue: "32k",
73 memorySection: "L1PSRAM"}],
74
75 ['l1DMode',{desc:"L1D Cache",
76 base:0x10F00000,
77 map : [["0k",0x0000],
78 ["4k",0x1000],
79 ["8k",0x2000],
80 ["16k",0x4000],
81 ["32k",0x8000]],
82 defaultValue: "32k",
83 memorySection: "L1DSRAM"}],
84
85 ['l2Mode',{desc:"L2 Cache",
86 base:0x10800000,
87 map : [["0k",0x0000],
88 ["32k",0x8000],
89 ["64k",0x10000],
90 ["128k",0x20000],
91 ["256k",0x40000]],
92 defaultValue: "0k",
93 memorySection: "IRAM"}],
94
95 ];
96
97 instance:
98 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
99
100 override config int minProgUnitSize = 1;
101 override config int minDataUnitSize = 1;
102 override config int dataWordSize = 4;
103
104 override config string cpuCore = "674";
105 override config string isa = "674";
106 override config string cpuCoreRevision = "1.0";
107
108 config xdc.platform.IPlatform.Memory memMap[string] = [
109
110 ["IRAM", {
111 comment: "Internal 256KB L2 memory",
112 name: "IRAM",
113 base: 0x10800000,
114 len: 0x40000,
115 space: "code/data",
116 access: "RWX"
117 }],
118
119 ["L1PSRAM", {
120 comment: "Internal 32KB L1 program memory",
121 name: "L1PSRAM",
122 base: 0x10E00000,
123 len: 0x8000,
124 space: "code",
125 access: "RWX"
126 }],
127
128 ["L1DSRAM", {
129 comment: "Internal 32KB L1 data memory",
130 name: "L1DSRAM",
131 base: 0x10F00000,
132 len: 0x8000,
133 space: "data",
134 access: "RW"
135 }],
136
137 ["OCMC", {
138 comment: "OCMC (On-chip RAM) (128KB)",
139 name: "OCMC",
140 base: 0x40300000,
141 len: 0x20000,
142 space: "code/data",
143 access: "RWX"
144 }],
145 ];
146 };