1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== IHimalaya.xdc ========
35 *
36 */
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== IHimalaya ========
41 * An interface implemented by all Himalaya devices
42 *
43 * This interface is defined to factor common data about all Himalaya devices
44 * into a single place; they are all the same from the configuration point of
45 * view.
46 */
47 metaonly interface IHimalaya inherits ti.catalog.ICpuDataSheet
48 {
49
50 config long cacheSizeL1[string] = [
51 ["0k", 0x0000],
52 ["4k", 0x1000],
53 ["8k", 0x2000],
54 ["16k", 0x4000],
55 ["32k", 0x8000],
56 ];
57
58 config long cacheSizeL2[string] = [
59 ["0k", 0x00000],
60 ["32k", 0x08000],
61 ["64k", 0x10000],
62 ["128k", 0x20000],
63 ["256k", 0x40000]
64 ];
65
66 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
67 ['l1PMode',{desc:"L1P Cache",
68 base:0xE00000,
69 map : [["0k",0x0000],
70 ["4k",0x1000],
71 ["8k",0x2000],
72 ["16k",0x4000],
73 ["32k",0x8000]],
74 defaultValue: "32k",
75 memorySection: "L1PSRAM"}],
76
77 ['l1DMode',{desc:"L1D Cache",
78 base:0xF00000,
79 map : [["0k",0x0000],
80 ["4k",0x1000],
81 ["8k",0x2000],
82 ["16k",0x4000],
83 ["32k",0x8000]],
84 defaultValue: "32k",
85 memorySection: "L1DSRAM"}],
86
87 ['l2Mode',{desc:"L2 Cache",
88 base:0x800000,
89 map : [["0k",0x0000],
90 ["32k",0x8000],
91 ["64k",0x10000],
92 ["128k", 0x20000],
93 ["256k", 0x40000]],
94 defaultValue: "0k",
95 memorySection: "IRAM"}],
96
97 ];
98
99 instance:
100
101 override config string cpuCore = "64x+";
102 override config string isa = "64P";
103 override config string cpuCoreRevision = "1.0";
104
105 override config int minProgUnitSize = 1;
106 override config int minDataUnitSize = 1;
107 override config int dataWordSize = 4;
108
109 /*!
110 * ======== memMap ========
111 * The default memory map for this device
112 */
113 config xdc.platform.IPlatform.Memory memMap[string] = [
114 ["IRAM", {
115 comment: "Internal 2MB UMAP0 memory",
116 name: "IRAM",
117 base: 0x800000,
118 len: 0x200000,
119 space: "code/data",
120 access: "RWX"
121 }],
122
123 ["L1PSRAM", {
124 comment: "Internal 32KB RAM/CACHE L1 program memory",
125 name: "L1PSRAM",
126 base: 0xE00000,
127 len: 0x008000,
128 space: "code",
129 access: "RWX"
130 }],
131
132 ["L1DSRAM", {
133 comment: "Internal 32KB RAM/CACHE L1 data memory",
134 name: "L1DSRAM",
135 base: 0xF00000,
136 len: 0x008000,
137 space: "data",
138 access: "RW"
139 }],
140
141 ];
142 };