metaonly interface ti.catalog.c6000.IDaVinci
index URL

An interface implemented by all DaVinci devices

This interface is defined to factor common data about all DaVinci devices into a single place; they are all the same from the configuration point of view.
XDCspec summary sourced in ti/catalog/c6000/IDaVinci.xdc
metaonly interface IDaVinci {  ...
// inherits ti.catalog.ICpuDataSheet
    // inherits xdc.platform.ICpuDataSheet
instance:  ...
XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
package ti.catalog.c6000;
 
metaonly interface IDaVinci inherits ICpuDataSheet {
module-wide config parameters
    readonly config ICacheInfo.CacheDesc cacheMap// [string] = [
        [
            'l1PMode',
            {
                desc: "L1P Cache",
                base: 0x11E08000,
                map: [
                    [
                        "0k",
                        0x0000
                    ],
                    [
                        "4k",
                        0x1000
                    ],
                    [
                        "8k",
                        0x2000
                    ],
                    [
                        "16k",
                        0x4000
                    ],
                    [
                        "32k",
                        0x8000
                    ]
                ],
                defaultValue: "32k",
                memorySection: "L1PSRAM"
            }
        ],
        [
            'l1DMode',
            {
                desc: "L1D Cache",
                base: 0x11F04000,
                map: [
                    [
                        "0k",
                        0x0000
                    ],
                    [
                        "4k",
                        0x1000
                    ],
                    [
                        "8k",
                        0x2000
                    ],
                    [
                        "16k",
                        0x4000
                    ],
                    [
                        "32k",
                        0x8000
                    ]
                ],
                defaultValue: "32k",
                memorySection: "L1DSRAM"
            }
        ],
        [
            'l2Mode',
            {
                desc: "L2 Cache",
                base: 0x11800000,
                map: [
                    [
                        "0k",
                        0x0000
                    ],
                    [
                        "32k",
                        0x8000
                    ],
                    [
                        "64k",
                        0x10000
                    ]
                ],
                defaultValue: "0k",
                memorySection: "IRAM"
            }
        ]
    ];
 
    config Long cacheSizeL1// [string] = [
        [
            "0k",
            0x0000
        ],
        [
            "4k",
            0x1000
        ],
        [
            "8k",
            0x2000
        ],
        [
            "16k",
            0x4000
        ],
        [
            "32k",
            0x8000
        ]
    ];
    config Long cacheSizeL2// [string] = [
        [
            "0k",
            0x00000
        ],
        [
            "32k",
            0x08000
        ],
        [
            "64k",
            0x10000
        ]
    ];
 
 
instance:
per-instance config parameters
    override config String cpuCore// A string identifying the CPU Core = "64x+";
    override config String cpuCoreRevision// A string that uniquely identifies a revision of the core = "1.0";
    override config Int dataWordSize// The size of an int on the target in 8-bit bytes = 4;
    config String deviceHeader// The optional header file that define device specific constants and structures;
    config IPlatform.Memory memMap// The default memory map for this device[string] = [
        [
            "IRAM",
            {
                comment: "Internal 64KB UMAP0 memory",
                name: "IRAM",
                base: 0x11800000,
                len: 0x00010000,
                space: "code/data",
                access: "RWX"
            }
        ],
        [
            "L1PSRAM",
            {
                comment: "Internal 32KB RAM/CACHE L1 program memory",
                name: "L1PSRAM",
                base: 0x11E08000,
                len: 0x00008000,
                space: "code",
                access: "RWX"
            }
        ],
        [
            "L1DSRAM",
            {
                comment: "Internal 80KB RAM/CACHE L1 data memory",
                name: "L1DSRAM",
                base: 0x11F04000,
                len: 0x00014000,
                space: "data",
                access: "RW"
            }
        ],
        [
            "ARM_RAM",
            {
                comment: "Internal ARM RAM memory",
                name: "ARM_RAM",
                base: 0x10008000,
                len: 0x00004000,
                space: "data",
                access: "RW"
            }
        ]
    ];
    override config Int minDataUnitSize// The minimum addressable data unit size in 8-bit bytes = 1;
    override config Int minProgUnitSize// The minimum addressable program unit size in 8-bit bytes = 1;
    config IPeripheral.Instance peripherals// A map of peripherals available on the device[string];
per-instance creation
    create// Create an instance-object(String revision);
per-instance functions
    function getMemoryMap// Get the memory map that corresponds to the values of the specified registers(registers);
    function getRegisterSet// The set of valid register names for this CPU();
}
 
config IDaVinci.cacheMap  // module-wide
index URL
XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
readonly config ICacheInfo.CacheDesc cacheMap[string] = [
    [
        'l1PMode',
        {
            desc: "L1P Cache",
            base: 0x11E08000,
            map: [
                [
                    "0k",
                    0x0000
                ],
                [
                    "4k",
                    0x1000
                ],
                [
                    "8k",
                    0x2000
                ],
                [
                    "16k",
                    0x4000
                ],
                [
                    "32k",
                    0x8000
                ]
            ],
            defaultValue: "32k",
            memorySection: "L1PSRAM"
        }
    ],
    [
        'l1DMode',
        {
            desc: "L1D Cache",
            base: 0x11F04000,
            map: [
                [
                    "0k",
                    0x0000
                ],
                [
                    "4k",
                    0x1000
                ],
                [
                    "8k",
                    0x2000
                ],
                [
                    "16k",
                    0x4000
                ],
                [
                    "32k",
                    0x8000
                ]
            ],
            defaultValue: "32k",
            memorySection: "L1DSRAM"
        }
    ],
    [
        'l2Mode',
        {
            desc: "L2 Cache",
            base: 0x11800000,
            map: [
                [
                    "0k",
                    0x0000
                ],
                [
                    "32k",
                    0x8000
                ],
                [
                    "64k",
                    0x10000
                ]
            ],
            defaultValue: "0k",
            memorySection: "IRAM"
        }
    ]
];
 
 
config IDaVinci.cacheSizeL1  // module-wide
index URL
XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
config Long cacheSizeL1[string] = [
    [
        "0k",
        0x0000
    ],
    [
        "4k",
        0x1000
    ],
    [
        "8k",
        0x2000
    ],
    [
        "16k",
        0x4000
    ],
    [
        "32k",
        0x8000
    ]
];
 
 
config IDaVinci.cacheSizeL2  // module-wide
index URL
XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
config Long cacheSizeL2[string] = [
    [
        "0k",
        0x00000
    ],
    [
        "32k",
        0x08000
    ],
    [
        "64k",
        0x10000
    ]
];
 
 
config IDaVinci.Params.cpuCore  // instance
index URL

A string identifying the CPU Core

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
override config String cpuCore = "64x+";
 
DETAILS
This uniquely identifies the instruction set that the CPU can decode and execute.
 
config IDaVinci.Params.cpuCoreRevision  // instance
index URL

A string that uniquely identifies a revision of the core

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
override config String cpuCoreRevision = "1.0";
 
 
config IDaVinci.Params.dataWordSize  // instance
index URL

The size of an int on the target in 8-bit bytes

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
override config Int dataWordSize = 4;
 
 
config IDaVinci.Params.deviceHeader  // instance
index URL

The optional header file that define device specific constants and structures

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
config String deviceHeader;
 
 
config IDaVinci.Params.memMap  // instance
index URL

The default memory map for this device

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
config IPlatform.Memory memMap[string] = [
    [
        "IRAM",
        {
            comment: "Internal 64KB UMAP0 memory",
            name: "IRAM",
            base: 0x11800000,
            len: 0x00010000,
            space: "code/data",
            access: "RWX"
        }
    ],
    [
        "L1PSRAM",
        {
            comment: "Internal 32KB RAM/CACHE L1 program memory",
            name: "L1PSRAM",
            base: 0x11E08000,
            len: 0x00008000,
            space: "code",
            access: "RWX"
        }
    ],
    [
        "L1DSRAM",
        {
            comment: "Internal 80KB RAM/CACHE L1 data memory",
            name: "L1DSRAM",
            base: 0x11F04000,
            len: 0x00014000,
            space: "data",
            access: "RW"
        }
    ],
    [
        "ARM_RAM",
        {
            comment: "Internal ARM RAM memory",
            name: "ARM_RAM",
            base: 0x10008000,
            len: 0x00004000,
            space: "data",
            access: "RW"
        }
    ]
];
 
 
config IDaVinci.Params.minDataUnitSize  // instance
index URL

The minimum addressable data unit size in 8-bit bytes

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
override config Int minDataUnitSize = 1;
 
 
config IDaVinci.Params.minProgUnitSize  // instance
index URL

The minimum addressable program unit size in 8-bit bytes

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
override config Int minProgUnitSize = 1;
 
 
config IDaVinci.Params.peripherals  // instance
index URL

A map of peripherals available on the device

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
config IPeripheral.Instance peripherals[string];
 
Static Instance Creation
index URL

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
create(String revision);
// Create an instance-object
ARGUMENTS
revision — a string that identifies revision of the CPU to be created.
DETAILS
A "data sheet" for a CPU allows one to get specific attributes for a CPU programatically; e.g., the memory map of the CPU.
Notice that we don't specify CPU registers when we create a a data-sheet; registers are provided as necessary to the other functions defined in this interface. This allows one to more easily get memory maps for several different setting of the registers, for example.
 
IDaVinci.getMemoryMap()  // instance
index URL

Get the memory map that corresponds to the values of the specified registers

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
function getMemoryMap(registers);
 
ARGUMENTS
registers — a hash of named registers to values at the time an executable is to be loaded (for example)
DETAILS
If a register is not specified and this register can affect the memory map, the register is assumed to be set to its reset value (the value of the register immediately after a CPU reset).
RETURNS
Returns an array of xdc.platform.IPlatform.Memory objects that represent the memory visible to an executable running on the CPU.
 
IDaVinci.getRegisterSet()  // instance
index URL

The set of valid register names for this CPU

XDCspec declarations sourced in ti/catalog/c6000/IDaVinci.xdc
function getRegisterSet();
 
DETAILS
This function returns the complete set of register names that may be passed to the getMemoryMap() function. This function is only used to enable one to write a "requires contract" for the getMemoryMap() function.
RETURNS
Returns an array of valid register names (strings) for this device; only names from this array are valid keys for the registers argument to getMemoryMap().
generated on Thu, 23 May 2019 00:23:46 GMT