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32
33 34 35 36
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== IDaVinci ========
41 * An interface implemented by all DaVinci devices
42 *
43 * This interface is defined to factor common data about all DaVinci devices
44 * into a single place; they are all the same from the configuration point of
45 * view.
46 */
47 metaonly interface IDaVinci inherits ti.catalog.ICpuDataSheet
48 {
49 config long cacheSizeL1[string] = [
50 ["0k", 0x0000],
51 ["4k", 0x1000],
52 ["8k", 0x2000],
53 ["16k", 0x4000],
54 ["32k", 0x8000],
55 ];
56
57 config long cacheSizeL2[string] = [
58 ["0k", 0x00000],
59 ["32k", 0x08000],
60 ["64k", 0x10000]
61 ];
62
63 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
64 ['l1PMode',{desc: "L1P Cache",
65 base: 0x11E08000,
66 map : [["0k",0x0000],
67 ["4k",0x1000],
68 ["8k",0x2000],
69 ["16k",0x4000],
70 ["32k",0x8000]],
71 defaultValue: "32k",
72 memorySection: "L1PSRAM"}],
73
74 ['l1DMode',{desc: "L1D Cache",
75 base: 0x11F04000,
76 map : [["0k",0x0000],
77 ["4k",0x1000],
78 ["8k",0x2000],
79 ["16k",0x4000],
80 ["32k",0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}],
83
84 ['l2Mode',{desc: "L2 Cache",
85 base: 0x11800000,
86 map : [["0k",0x0000],
87 ["32k",0x8000],
88 ["64k",0x10000]],
89 defaultValue: "0k",
90 memorySection: "IRAM"}],
91
92 ];
93
94 instance:
95
96 override config string cpuCore = "64x+";
97 override config string isa = "64P";
98 override config string cpuCoreRevision = "1.0";
99
100 override config int minProgUnitSize = 1;
101 override config int minDataUnitSize = 1;
102 override config int dataWordSize = 4;
103
104 /*!
105 * ======== memMap ========
106 * The default memory map for this device
107 */
108 config xdc.platform.IPlatform.Memory memMap[string] = [
109 ["IRAM", {
110 comment: "Internal 64KB UMAP0 memory",
111 name: "IRAM",
112 base: 0x11800000,
113 len: 0x00010000,
114 space: "code/data",
115 access: "RWX"
116 }],
117
118 ["L1PSRAM", {
119 comment: "Internal 32KB RAM/CACHE L1 program memory",
120 name: "L1PSRAM",
121 base: 0x11E08000,
122 len: 0x00008000,
123 space: "code",
124 access: "RWX"
125 }],
126
127 ["L1DSRAM", {
128 comment: "Internal 80KB RAM/CACHE L1 data memory",
129 name: "L1DSRAM",
130 base: 0x11F04000,
131 len: 0x00014000,
132 space: "data",
133 access: "RW"
134 }],
135
136 ["ARM_RAM", {
137 comment: "Internal ARM RAM memory",
138 name: "ARM_RAM",
139 base: 0x10008000,
140 len: 0x00004000,
141 space: "data",
142 access: "RW"
143 }],
144 ];
145 };