1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== DMA37XX.xdc ========
35 */
36 package ti.catalog.c6000;
37
38 /*!
39 * ======== DM37XX ========
40 * An interface implemented by DM37XX devices.
41 *
42 */
43 metaonly module DM37XX inherits ti.catalog.ICpuDataSheet
44 {
45
46 config long cacheSizeL1[string] = [
47 ["0k", 0x0000],
48 ["4k", 0x1000],
49 ["8k", 0x2000],
50 ["16k", 0x4000],
51 ["32k", 0x8000],
52 ];
53
54 config long cacheSizeL2[string] = [
55 ["0k", 0x00000],
56 ["32k", 0x08000],
57 ["64k", 0x10000]
58 ];
59
60 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
61 ['l1PMode',{desc:"L1P Cache",
62 base: 0x11E00000,
63 map : [["0k",0x0000],
64 ["4k",0x1000],
65 ["8k",0x2000],
66 ["16k",0x4000],
67 ["32k",0x8000]],
68 defaultValue: "32k",
69 memorySection: "L1PSRAM"}],
70
71 ['l1DMode',{desc:"L1D Cache",
72 base: 0x11F00000,
73 map : [["0k",0x0000],
74 ["4k",0x1000],
75 ["8k",0x2000],
76 ["16k",0x4000],
77 ["32k",0x8000]],
78 defaultValue: "32k",
79 memorySection: "L1DSRAM"}],
80
81 ['l2Mode',{desc:"L2 Cache",
82 base: 0x11800000,
83 map : [["0k",0x0000],
84 ["32k",0x8000],
85 ["64k",0x10000]],
86 defaultValue: "0k",
87 memorySection: "IRAM"}],
88
89 ];
90
91 instance:
92 override config int minProgUnitSize = 1;
93 override config int minDataUnitSize = 1;
94 override config int dataWordSize = 4;
95
96 override config string cpuCore = "64x+";
97 override config string isa = "64P";
98 override config string cpuCoreRevision = "1.0";
99
100 config xdc.platform.IPlatform.Memory memMap[string] = [
101 ["IROM", {
102 comment: "Internal 16KB L2 ROM",
103 name: "IROM",
104 base: 0x007E0000,
105 len: 0x00004000,
106 space: "code/data",
107 access: "RX"
108 }],
109
110 ["IRAM", {
111 comment: "Internal 96KB L2 memory",
112 name: "IRAM",
113 base: 0x007F8000,
114 len: 0x00018000,
115 space: "code/data",
116 access: "RWX"
117 }],
118
119 ["L1PSRAM", {
120 comment: "Internal 32KB L1 program memory",
121 name: "L1PSRAM",
122 base: 0x00E00000,
123 len: 0x00008000,
124 space: "code",
125 access: "RWX"
126 }],
127
128 ["L1DSRAM", {
129 comment: "Internal 80KB L1 data memory",
130 name: "L1DSRAM",
131 base: 0x00F04000,
132 len: 0x00014000,
133 space: "data",
134 access: "RW"
135 }],
136 ];
137 };