1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== Arctic.xdc ========
35 *
36 */
37
38 /*!
39 * ======== Arctic ========
40 * The Arctic device data sheet module.
41 *
42 * This module implements the ICpuDataSheet interface and is
43 * used by platforms to obtain "data sheet" information about this device.
44 */
45 metaonly module Arctic inherits ti.catalog.ICpuDataSheet
46 {
47 config long cacheSizeL1[string] = [
48 ["0k", 0x0000],
49 ["4k", 0x1000],
50 ["8k", 0x2000],
51 ["16k", 0x4000],
52 ["32k", 0x8000],
53 ];
54
55 config long cacheSizeL2[string] = [
56 ["0k", 0x00000],
57 ["32k", 0x08000],
58 ["64k", 0x10000],
59 ["128k", 0x20000],
60 ["256k", 0x40000],
61 ["512k", 0x80000],
62 ];
63
64 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
65 ['l1PMode',{desc:"L1P Cache",
66 base: 0xE00000,
67 map : [["0k",0x0000],
68 ["4k",0x1000],
69 ["8k",0x2000],
70 ["16k",0x4000],
71 ["32k",0x8000]],
72 defaultValue: "32k",
73 memorySection: "L1PSRAM"}],
74
75 ['l1DMode',{desc:"L1D Cache",
76 base: 0xF00000,
77 map : [["0k",0x0000],
78 ["4k",0x1000],
79 ["8k",0x2000],
80 ["16k",0x4000],
81 ["32k",0x8000]],
82 defaultValue: "32k",
83 memorySection: "L1DSRAM"}],
84
85 ['l2Mode',{desc:"L2 Cache",
86 base: 0x800000,
87 map : [["0k",0x0000],
88 ["32k",0x8000],
89 ["64k",0x10000],
90 ["128k",0x20000],
91 ["256k",0x40000],
92 ["512k",0x80000]],
93 defaultValue: "0k",
94 memorySection: "IRAM"}],
95 ];
96
97 instance:
98
99 override config string cpuCore = "C674";
100 override config string isa = "674";
101 override config string cpuCoreRevision = "1.0";
102
103 override config int minProgUnitSize = 1;
104 override config int minDataUnitSize = 1;
105 override config int dataWordSize = 4;
106
107 /*!
108 * ======== memMap ========
109 * The default memory map for this device
110 */
111 config xdc.platform.IPlatform.Memory memMap[string] = [
112 ["IRAM", {
113 comment: "Internal 512KB L2 RAM/cache memory",
114 name: "IRAM",
115 base: 0x00800000,
116 len: 0x00080000,
117 space: "code/data",
118 access: "RWX"
119 }],
120
121 ["L1PSRAM", {
122 comment: "Internal 32KB L1 program/cache memory",
123 name: "L1PSRAM",
124 base: 0x00E00000,
125 len: 0x00008000,
126 space: "code",
127 access: "RX"
128 }],
129
130 ["L1DSRAM", {
131 comment: "Internal 32KB L1 data/cache memory",
132 name: "L1DSRAM",
133 base: 0x00F00000,
134 len: 0x00008000,
135 space: "data",
136 access: "RW"
137 }],
138
139 ["L3MEM", {
140 comment: "1MB L3 Memory",
141 name: "L3MEM",
142 base: 0x40300000,
143 len: 0x00100000,
144 space: "code/data",
145 access: "RWX"
146 }],
147
148 ["DMEM", {
149 comment: "ARP32 Internal data memory",
150 name: "DMEM",
151 base: 0x59020000,
152 len: 0x8000,
153 space: "data",
154 access: "RW"
155 }],
156 ];
157 };