TI Cortex-M4 Timing Benchmarks
Target Platform: ti.platforms.simplelink:CC3200:1
Tool Chain Version: 18.1.2
BIOS Version: bios_6_73_00_11_eng
XDCTools Version: xdctools_3_50_07_20_core
Benchmark | Cycles |
---|---|
Interrupt Latency | 127 |
Hwi_restore() | 11 |
Hwi_disable() | 15 |
Hwi dispatcher prolog | 103 |
Hwi dispatcher epilog | 237 |
Hwi dispatcher | 334 |
Hardware Interrupt to Blocked Task | 552 |
Hardware Interrupt to Software Interrupt | 375 |
Swi_enable() | 81 |
Swi_disable() | 11 |
Post Software Interrupt Again | 38 |
Post Software Interrupt without Context Switch | 102 |
Post Software Interrupt with Context Switch | 206 |
Create a New Task without Context Switch | 2748 |
Set a Task Priority without a Context Switch | 172 |
Task_yield() | 217 |
Post Semaphore No Waiting Task | 95 |
Post Semaphore No Task Switch | 200 |
Post Semaphore with Task Switch | 269 |
Pend on Semaphore No Context Switch | 83 |
Pend on Semaphore with Task Switch | 288 |
Clock_getTicks() | 8 |
POSIX Create a New Task without Context Switch | 5058 |
POSIX Set a Task Priority without a Context Switch | 238 |
POSIX Post Semaphore No Waiting Task | 108 |
POSIX Post Semaphore No Task Switch | 216 |
POSIX Post Semaphore with Task Switch | 285 |
POSIX Pend on Semaphore No Context Switch | 95 |
POSIX Pend on Semaphore with Task Switch | 306 |
The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.
To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.