IAR Cortex-M4 Timing Benchmarks
Target Platform: ti.platforms.tiva:TM4C123GH6PM:1
Tool Chain Version: 8.20.2.58
BIOS Version: bios_6_73_00_11_eng
XDCTools Version: xdctools_3_50_07_20_core
Benchmark | Cycles |
---|---|
Interrupt Latency | 116 |
Hwi_restore() | 7 |
Hwi_disable() | 9 |
Hwi dispatcher prolog | 95 |
Hwi dispatcher epilog | 200 |
Hwi dispatcher | 285 |
Hardware Interrupt to Blocked Task | 458 |
Hardware Interrupt to Software Interrupt | 310 |
Swi_enable() | 58 |
Swi_disable() | 11 |
Post Software Interrupt Again | 20 |
Post Software Interrupt without Context Switch | 81 |
Post Software Interrupt with Context Switch | 165 |
Create a New Task without Context Switch | 1960 |
Set a Task Priority without a Context Switch | 148 |
Task_yield() | 185 |
Post Semaphore No Waiting Task | 66 |
Post Semaphore No Task Switch | 161 |
Post Semaphore with Task Switch | 217 |
Pend on Semaphore No Context Switch | 58 |
Pend on Semaphore with Task Switch | 242 |
Clock_getTicks() | 9 |
POSIX Create a New Task without Context Switch | 3452 |
POSIX Set a Task Priority without a Context Switch | 189 |
POSIX Post Semaphore No Waiting Task | 79 |
POSIX Post Semaphore No Task Switch | 173 |
POSIX Post Semaphore with Task Switch | 224 |
POSIX Pend on Semaphore No Context Switch | 47 |
POSIX Pend on Semaphore with Task Switch | 245 |
The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.