GCC Cortex-A9 with hard FP Timing Benchmarks

Target Platform: ti.platforms.sdp4430

Tool Chain Version: 7.2.1

BIOS Version: bios_6_73_00_11_eng

XDCTools Version: xdctools_3_50_07_20_core

Benchmark	Cycles
Interrupt Latency	354
Hwi_restore()	9
Hwi_disable()	5
Hwi dispatcher prolog	196
Hwi dispatcher epilog	167
Hwi dispatcher	368
Hardware Interrupt to Blocked Task	592
Hardware Interrupt to Software Interrupt	401
Swi_enable()	62
Swi_disable()	1
Post Software Interrupt Again	25
Post Software Interrupt without Context Switch	82
Post Software Interrupt with Context Switch	152
Create a New Task without Context Switch	1933
Set a Task Priority without a Context Switch	103
Task_yield()	225
Post Semaphore No Waiting Task	82
Post Semaphore No Task Switch	167
Post Semaphore with Task Switch	266
Pend on Semaphore No Context Switch	36
Pend on Semaphore with Task Switch	267
Clock_getTicks()	7
POSIX Create a New Task without Context Switch	3619
POSIX Set a Task Priority without a Context Switch	99
POSIX Post Semaphore No Waiting Task	85
POSIX Post Semaphore No Task Switch	172
POSIX Post Semaphore with Task Switch	293
POSIX Pend on Semaphore No Context Switch	47
POSIX Pend on Semaphore with Task Switch	268

As the timer used to run these benchmarks is run at 1/2 the CPU frequency, an deviation of +-2 cycles is to be expected.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.