IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 8.20.2.58

BIOS Version: bios_6_73_00_11_eng

XDCTools Version: xdctools_3_50_07_20_core

Benchmark	Cycles
Interrupt Latency	148
Hwi_restore()	14
Hwi_disable()	16
Hwi dispatcher prolog	123
Hwi dispatcher epilog	255
Hwi dispatcher	368
Hardware Interrupt to Blocked Task	592
Hardware Interrupt to Software Interrupt	401
Swi_enable()	75
Swi_disable()	17
Post Software Interrupt Again	24
Post Software Interrupt without Context Switch	105
Post Software Interrupt with Context Switch	209
Create a New Task without Context Switch	2630
Set a Task Priority without a Context Switch	191
Task_yield()	238
Post Semaphore No Waiting Task	84
Post Semaphore No Task Switch	207
Post Semaphore with Task Switch	277
Pend on Semaphore No Context Switch	79
Pend on Semaphore with Task Switch	311
Clock_getTicks()	14
POSIX Create a New Task without Context Switch	4691
POSIX Set a Task Priority without a Context Switch	247
POSIX Post Semaphore No Waiting Task	105
POSIX Post Semaphore No Task Switch	230
POSIX Post Semaphore with Task Switch	296
POSIX Pend on Semaphore No Context Switch	61
POSIX Pend on Semaphore with Task Switch	314

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.