TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 18.1.1

BIOS Version: bios_6_70_00_18_eng

XDCTools Version: xdctools_3_50_04_43_core

Benchmark	Cycles
Interrupt Latency	126
Hwi_restore()	11
Hwi_disable()	15
Hwi dispatcher prolog	104
Hwi dispatcher epilog	240
Hwi dispatcher	338
Hardware Interrupt to Blocked Task	641
Hardware Interrupt to Software Interrupt	377
Swi_enable()	82
Swi_disable()	11
Post Software Interrupt Again	37
Post Software Interrupt without Context Switch	102
Post Software Interrupt with Context Switch	204
Create a New Task without Context Switch	2826
Set a Task Priority without a Context Switch	188
Task_yield()	269
Post Semaphore No Waiting Task	93
Post Semaphore No Task Switch	248
Post Semaphore with Task Switch	357
Pend on Semaphore No Context Switch	87
Pend on Semaphore with Task Switch	345
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	5048
POSIX Set a Task Priority without a Context Switch	256
POSIX Post Semaphore No Waiting Task	106
POSIX Post Semaphore No Task Switch	263
POSIX Post Semaphore with Task Switch	372
POSIX Pend on Semaphore No Context Switch	98
POSIX Pend on Semaphore with Task Switch	365

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.