TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 18.1.1

BIOS Version: bios_6_70_00_18_eng

XDCTools Version: xdctools_3_50_04_43_core

Benchmark	Cycles
Interrupt Latency	135
Hwi_restore()	6
Hwi_disable()	8
Hwi dispatcher prolog	114
Hwi dispatcher epilog	211
Hwi dispatcher	315
Hardware Interrupt to Blocked Task	564
Hardware Interrupt to Software Interrupt	332
Swi_enable()	60
Swi_disable()	8
Post Software Interrupt Again	30
Post Software Interrupt without Context Switch	84
Post Software Interrupt with Context Switch	163
Create a New Task without Context Switch	2192
Set a Task Priority without a Context Switch	144
Task_yield()	240
Post Semaphore No Waiting Task	72
Post Semaphore No Task Switch	192
Post Semaphore with Task Switch	311
Pend on Semaphore No Context Switch	62
Pend on Semaphore with Task Switch	297
Clock_getTicks()	7
POSIX Create a New Task without Context Switch	3829
POSIX Set a Task Priority without a Context Switch	189
POSIX Post Semaphore No Waiting Task	81
POSIX Post Semaphore No Task Switch	204
POSIX Post Semaphore with Task Switch	324
POSIX Pend on Semaphore No Context Switch	74
POSIX Pend on Semaphore with Task Switch	310

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.