IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 8.20.2.58

BIOS Version: bios_6_70_00_18_eng

XDCTools Version: xdctools_3_50_04_43_core

Benchmark	Cycles
Interrupt Latency	116
Hwi_restore()	7
Hwi_disable()	9
Hwi dispatcher prolog	95
Hwi dispatcher epilog	200
Hwi dispatcher	285
Hardware Interrupt to Blocked Task	509
Hardware Interrupt to Software Interrupt	310
Swi_enable()	58
Swi_disable()	11
Post Software Interrupt Again	20
Post Software Interrupt without Context Switch	81
Post Software Interrupt with Context Switch	165
Create a New Task without Context Switch	1990
Set a Task Priority without a Context Switch	156
Task_yield()	213
Post Semaphore No Waiting Task	66
Post Semaphore No Task Switch	192
Post Semaphore with Task Switch	268
Pend on Semaphore No Context Switch	58
Pend on Semaphore with Task Switch	270
Clock_getTicks()	9
POSIX Create a New Task without Context Switch	3453
POSIX Set a Task Priority without a Context Switch	197
POSIX Post Semaphore No Waiting Task	79
POSIX Post Semaphore No Task Switch	204
POSIX Post Semaphore with Task Switch	275
POSIX Pend on Semaphore No Context Switch	47
POSIX Pend on Semaphore with Task Switch	273

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.