IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 8.20.2.58

BIOS Version: bios_6_70_00_18_eng

XDCTools Version: xdctools_3_50_04_43_core

Benchmark	Cycles
Interrupt Latency	145
Hwi_restore()	15
Hwi_disable()	17
Hwi dispatcher prolog	124
Hwi dispatcher epilog	254
Hwi dispatcher	367
Hardware Interrupt to Blocked Task	650
Hardware Interrupt to Software Interrupt	401
Swi_enable()	76
Swi_disable()	17
Post Software Interrupt Again	26
Post Software Interrupt without Context Switch	103
Post Software Interrupt with Context Switch	209
Create a New Task without Context Switch	2655
Set a Task Priority without a Context Switch	200
Task_yield()	265
Post Semaphore No Waiting Task	84
Post Semaphore No Task Switch	240
Post Semaphore with Task Switch	334
Pend on Semaphore No Context Switch	78
Pend on Semaphore with Task Switch	345
Clock_getTicks()	14
POSIX Create a New Task without Context Switch	4710
POSIX Set a Task Priority without a Context Switch	255
POSIX Post Semaphore No Waiting Task	104
POSIX Post Semaphore No Task Switch	261
POSIX Post Semaphore with Task Switch	352
POSIX Pend on Semaphore No Context Switch	62
POSIX Pend on Semaphore with Task Switch	346

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.