GCC Cortex-A9 with hard FP Timing Benchmarks

Target Platform: ti.platforms.sdp4430

Tool Chain Version: 7.2.1

BIOS Version: bios_6_70_00_18_eng

XDCTools Version: xdctools_3_50_04_43_core

Benchmark	Cycles
Interrupt Latency	313
Hwi_restore()	8
Hwi_disable()	4
Hwi dispatcher prolog	194
Hwi dispatcher epilog	166
Hwi dispatcher	364
Hardware Interrupt to Blocked Task	614
Hardware Interrupt to Software Interrupt	368
Swi_enable()	61
Swi_disable()	12
Post Software Interrupt Again	24
Post Software Interrupt without Context Switch	81
Post Software Interrupt with Context Switch	151
Create a New Task without Context Switch	1886
Set a Task Priority without a Context Switch	102
Task_yield()	245
Post Semaphore No Waiting Task	81
Post Semaphore No Task Switch	181
Post Semaphore with Task Switch	301
Pend on Semaphore No Context Switch	35
Pend on Semaphore with Task Switch	287
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	3557
POSIX Set a Task Priority without a Context Switch	88
POSIX Post Semaphore No Waiting Task	110
POSIX Post Semaphore No Task Switch	209
POSIX Post Semaphore with Task Switch	337
POSIX Pend on Semaphore No Context Switch	46
POSIX Pend on Semaphore with Task Switch	294

As the timer used to run these benchmarks is run at 1/2 the CPU frequency, an deviation of +-2 cycles is to be expected.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.