Texas Instruments

Table of Contents

TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 16.9.3

BIOS Version: bios_6_51_00_11_eng

XDCTools Version: xdctools_3_50_02_20_core

Benchmark Cycles
Interrupt Latency 125
Hwi_restore() 9
Hwi_disable() 13
Hwi dispatcher prolog 102
Hwi dispatcher epilog 234
Hwi dispatcher 330
Hardware Interrupt to Blocked Task 551
Hardware Interrupt to Software Interrupt 373
Swi_enable() 81
Swi_disable() 11
Post Software Interrupt Again 37
Post Software Interrupt without Context Switch 101
Post Software Interrupt with Context Switch 200
Create a New Task without Context Switch 1986
Set a Task Priority without a Context Switch 171
Task_yield() 216
Post Semaphore No Waiting Task 51
Post Semaphore No Task Switch 200
Post Semaphore with Task Switch 271
Pend on Semaphore No Context Switch 83
Pend on Semaphore with Task Switch 288
Clock_getTicks() 8
POSIX Create a New Task without Context Switch 4064
POSIX Set a Task Priority without a Context Switch 242
POSIX Post Semaphore No Waiting Task 67
POSIX Post Semaphore No Task Switch 217
POSIX Post Semaphore with Task Switch 284
POSIX Pend on Semaphore No Context Switch 94
POSIX Pend on Semaphore with Task Switch 304

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.