Texas Instruments

Table of Contents

TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 16.9.3

BIOS Version: bios_6_51_00_11_eng

XDCTools Version: xdctools_3_50_02_20_core

Benchmark Cycles
Interrupt Latency 135
Hwi_restore() 6
Hwi_disable() 8
Hwi dispatcher prolog 114
Hwi dispatcher epilog 211
Hwi dispatcher 315
Hardware Interrupt to Blocked Task 499
Hardware Interrupt to Software Interrupt 324
Swi_enable() 60
Swi_disable() 8
Post Software Interrupt Again 30
Post Software Interrupt without Context Switch 82
Post Software Interrupt with Context Switch 155
Create a New Task without Context Switch 1559
Set a Task Priority without a Context Switch 141
Task_yield() 202
Post Semaphore No Waiting Task 42
Post Semaphore No Task Switch 155
Post Semaphore with Task Switch 246
Pend on Semaphore No Context Switch 64
Pend on Semaphore with Task Switch 262
Clock_getTicks() 7
POSIX Create a New Task without Context Switch 3057
POSIX Set a Task Priority without a Context Switch 187
POSIX Post Semaphore No Waiting Task 51
POSIX Post Semaphore No Task Switch 168
POSIX Post Semaphore with Task Switch 258
POSIX Pend on Semaphore No Context Switch 76
POSIX Pend on Semaphore with Task Switch 273

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.