Texas Instruments

Table of Contents

TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432P401R:1

Tool Chain Version: 16.9.3

BIOS Version: bios_6_51_00_11_eng

XDCTools Version: xdctools_3_50_02_20_core

Benchmark Cycles
Interrupt Latency 128
Hwi_restore() 6
Hwi_disable() 7
Hwi dispatcher prolog 122
Hwi dispatcher epilog 223
Hwi dispatcher 333
Hardware Interrupt to Blocked Task 525
Hardware Interrupt to Software Interrupt 350
Swi_enable() 64
Swi_disable() 9
Post Software Interrupt Again 30
Post Software Interrupt without Context Switch 89
Post Software Interrupt with Context Switch 170
Create a New Task without Context Switch 1637
Set a Task Priority without a Context Switch 140
Task_yield() 206
Post Semaphore No Waiting Task 43
Post Semaphore No Task Switch 164
Post Semaphore with Task Switch 255
Pend on Semaphore No Context Switch 65
Pend on Semaphore with Task Switch 269
Clock_getTicks() 8
POSIX Create a New Task without Context Switch 3210
POSIX Set a Task Priority without a Context Switch 186
POSIX Post Semaphore No Waiting Task 52
POSIX Post Semaphore No Task Switch 175
POSIX Post Semaphore with Task Switch 265
POSIX Pend on Semaphore No Context Switch 78
POSIX Pend on Semaphore with Task Switch 281

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.