Texas Instruments

Table of Contents

IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 8.11.1.47

BIOS Version: bios_6_51_00_11_eng

XDCTools Version: xdctools_3_50_02_20_core

Benchmark Cycles
Interrupt Latency 149
Hwi_restore() 13
Hwi_disable() 16
Hwi dispatcher prolog 115
Hwi dispatcher epilog 245
Hwi dispatcher 351
Hardware Interrupt to Blocked Task 575
Hardware Interrupt to Software Interrupt 394
Swi_enable() 74
Swi_disable() 16
Post Software Interrupt Again 25
Post Software Interrupt without Context Switch 101
Post Software Interrupt with Context Switch 210
Create a New Task without Context Switch 1943
Set a Task Priority without a Context Switch 188
Task_yield() 233
Post Semaphore No Waiting Task 51
Post Semaphore No Task Switch 198
Post Semaphore with Task Switch 272
Pend on Semaphore No Context Switch 75
Pend on Semaphore with Task Switch 304
Clock_getTicks() 13
POSIX Create a New Task without Context Switch 3786
POSIX Set a Task Priority without a Context Switch 248
POSIX Post Semaphore No Waiting Task 73
POSIX Post Semaphore No Task Switch 224
POSIX Post Semaphore with Task Switch 290
POSIX Pend on Semaphore No Context Switch 61
POSIX Pend on Semaphore with Task Switch 310

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.