Texas Instruments

Table of Contents

IAR Cortex-M3 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC1350:1

Tool Chain Version: 8.11.1.47

BIOS Version: bios_6_51_00_11_eng

XDCTools Version: xdctools_3_50_02_20_core

Benchmark Cycles
Interrupt Latency 153
Hwi_restore() 15
Hwi_disable() 16
Hwi dispatcher prolog 122
Hwi dispatcher epilog 205
Hwi dispatcher 316
Hardware Interrupt to Blocked Task 541
Hardware Interrupt to Software Interrupt 390
Swi_enable() 75
Swi_disable() 18
Post Software Interrupt Again 37
Post Software Interrupt without Context Switch 102
Post Software Interrupt with Context Switch 213
Create a New Task without Context Switch 4637
Set a Task Priority without a Context Switch 199
Task_yield() 213
Post Semaphore No Waiting Task 60
Post Semaphore No Task Switch 202
Post Semaphore with Task Switch 266
Pend on Semaphore No Context Switch 71
Pend on Semaphore with Task Switch 300
Clock_getTicks() 314
POSIX Create a New Task without Context Switch 7356
POSIX Set a Task Priority without a Context Switch 277
POSIX Post Semaphore No Waiting Task 73
POSIX Post Semaphore No Task Switch 215
POSIX Post Semaphore with Task Switch 277
POSIX Pend on Semaphore No Context Switch 85
POSIX Pend on Semaphore with Task Switch 313

The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.