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32 33 34 35
36
37 package ti.sysbios.family.arp32;
38
39 /*!
40 * ======== CTM ========
41 * Counter Timer Module Device Definitions.
42 *
43 * For Ducati SYS/BIOS applications,
44 * Counter/timer 0 is assigned to core 0's Timer 0 interrupt 18
45 * Counter/timer 1 is assigned to core 1's Timer 0 interrupt 22
46 * Counters 2/3 are assigned to core 0's TimestampProvider
47 * Counters 4/5 are assigned to core 1's TimestampProvider
48 * Counters 6,7 are for application use.
49 *
50 * Counters 2/3 and 4/5 are in chained mode and started simultaneously
51 * by core 0 so that both cores timestamps are in sync with each other
52 * AND both chained timers have independent SHADOW registers to guarantee
53 * 64bit counter reading coherency.
54 */
55
56 module CTM
57 {
58 /*!
59 * Counter Timer Module
60 * Physical Base address is 0x55080400
61 * Auto-configured virtual Base address is 0x40000400
62 */
63 struct CTM {
64 UInt32 CTCNTL; /*! 0x0000 */
65 UInt32 RES_04 [7]; /*! 0x0004 - 0x0020 */
66 UInt32 CTSTMCNTL; /*! 0x0020 */
67 UInt32 CTSTMMSTID; /*! 0x0024 */
68 UInt32 CTSTMINTVL; /*! 0x0028 */
69 UInt32 CTSTMSEL0; /*! 0x002C */
70 UInt32 CTSTMSEL1; /*! 0x0030 */
71 UInt32 RES_34 [3]; /*! 0x0034 - 0x0040 */
72 UInt32 TINTVLR[8]; /*! 0x0040 - 0x0060 */
73 UInt32 RES_60 [7]; /*! 0x0060 - 0x007C */
74 UInt32 CTNUMDBG; /*! 0x007C */
75 UInt32 CTDBGSGL [8]; /*! 0x0080 - 0x00A0 */
76 UInt32 RES_A0 [20]; /*! 0x00A0 - 0x00F0 */
77 UInt32 CTGNBL [2]; /*! 0x00F0 - 0x00F8 */
78 UInt32 CTGRST [2]; /*! 0x00F8 - 0x0100 */
79 UInt32 CTCR [32]; /*! 0x0100 - 0x0180 */
80 UInt32 CTCNTR [32]; /*! 0x0180 - 0x0200 */
81 }
82
83 /*!
84 * Physical CTM Device.
85 * Short name is "CTM_ctm"
86 * Long name is "ti_sysbios_family_arp32.CTM_ctm"
87 */
88 extern volatile CTM ctm;
89 }
90