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36
37 package ti.sysbios.family.arm.msp432.init;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Assert;
41
42 /*!
43 * ======== Boot ========
44 * MSP432 device Boot Support.
45 *
46 * The Boot module supports boot initialization for MSP432 devices.
47 * A special boot init function is created based on the configuration
48 * settings for this module. This function is hooked into the
49 * xdc.runtime.Reset.fxns[] array and called very early at boot time.
50 *
51 * The code to support the boot module is placed in a separate section
52 * named `".text:.bootCodeSection"` to allow placement of this section in
53 * the linker .cmd file if necessary. This section is a subsection of the
54 * `".text"` section so this code will be placed into the .text section unless
55 * explicitly placed, either through
56 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
57 * command file.
58 */
59 @Template("./Boot.xdt")
60 module Boot
61 {
62 /*! clock speed setting */
63 enum SpeedOpt {
64 SpeedOpt_Low = 0,
65 SpeedOpt_Medium = 1,
66 SpeedOpt_High = 2
67 };
68
69 metaonly struct ModuleView {
70 Bool configureClocks;
71 Bool disableWatchdog;
72 }
73
74 @Facet
75 metaonly config ViewInfo.Instance rovViewInfo =
76 ViewInfo.create({
77 viewMap: [
78 [
79 'Module',
80 {
81 type: ViewInfo.MODULE,
82 viewInitFxn: 'viewInitModule',
83 structName: 'ModuleView'
84 }
85 ],
86 ]
87 });
88
89 /*!
90 * Clock configuration flag, default is true.
91 *
92 * Set to false to disable clock configuration.
93 *
94 * Clock configuration will setup the clock system (CS), VCORE, and
95 * Flash wait states appropriately, for one of three different device
96 * speed options, as selected by `{@link #speedSelect}`.
97 */
98 metaonly config Bool configureClocks = true;
99
100 /*!
101 * Clock speed selection, default is SpeedOpt_High.
102 *
103 * This enumeration is used to select one of three different speed options
104 * that will be configured when `{@link #configureClocks}` is set to
105 * "true".
106 *
107 * @p(code)
108 * SpeedOpt_High will configure:
109 * MCLK = 48MHz from DCO, HFXT, or external clock
110 * HSMCLK = 24MHz from DCO, HFXT, or external clock
111 * SMCLK = 12MHz from DCO, HFXT, or external clock
112 * ACLK = 32KHz from REFOCLK, LFXT, or external clock
113 * BCLK = 32KHz from REFOCLK, LFXT, or external clock
114 * VCORE = 1 (AM1_LDO mode)
115 * Flash BNK0 and BNK1 read wait states = 1 (MSP432P401xx)
116 * Flash BNK0 and BNK1 read wait states = 3 (MSP432P4x1xl/MSP432P4x1xT)
117 *
118 * SpeedOpt_Medium will configure:
119 * MCLK = 24MHz from DCO, HFXT, or external clock
120 * HSMCLK = 6MHz from DCO, HFXT, or external clock
121 * SMCLK = 6MHz from DCO, HFXT, or external clock
122 * ACLK = 32KHz from REFOCLK, LFXT, or external clock
123 * BCLK = 32KHz from REFOCLK, LFXT, or external clock
124 * VCORE = 1 (AM1_LDO mode)
125 * Flash BNK0 and BNK1 read wait states = 1 (for all device variants)
126 *
127 * SpeedOpt_Low will configure:
128 * MCLK = 12MHz from DCO, HFXT, or external clock
129 * HSMCLK = 3MHz from DCO, HFXT, or external clock
130 * SMCLK = 3MHz from DCO, HFXT, or external clock
131 * ACLK = 32KHz from REFOCLK, LFXT, or external clock
132 * BCLK = 32KHz from REFOCLK, LFXT, or external clock
133 * VCORE = 0 (AM0_LDO mode)
134 * Flash BNK0 and BNK1 read wait states = 0 (MSP432P401xx)
135 * Flash BNK0 and BNK1 read wait states = 1 (MSP432P4x1xl/MSP432P4x1xT)
136 * @p
137 */
138 metaonly config SpeedOpt speedSelect = SpeedOpt_High;
139
140 /*!
141 * Enable LF crystal (LFXT) flag, default is false.
142 *
143 * If an external 32768-Hz LF crystal is available, set this flag to
144 * true to startup and enable the LFXT, for use as the ACLK and BCLK
145 * clock sources.
146 */
147 config Bool enableLFXT = false;
148
149 /*!
150 * LF crystal bypass flag, default is false.
151 *
152 * As an alternative to LFXT-sourced clocks, an external 32768-Hz square
153 * wave can be applied to LFXIN, to be used as the ACLK and BCLK clock
154 * sources.
155 *
156 * To enable this mode, set Boot.enableLFXT to true to enable the LFXT
157 * pins, and set Boot.bypassLFXT to true to disable the LFXT oscillator.
158 */
159 config Bool bypassLFXT = false;
160
161 /*!
162 * Enable HF crystal (HFXT) flag, default is false.
163 *
164 * If an external 48-MHz HFXT crystal is available, set this flag to
165 * true to startup and enable the HFXT, for use as the MCLK, HSMCLK, and
166 * SMCLK clock sources.
167 */
168 config Bool enableHFXT = false;
169
170 /*!
171 * HF crystal bypass flag, default is false.
172 *
173 * As an alternative to HFXT-sourced clocks, an external 48-MHz square
174 * wave can be applied to HFXIN, to be used as the MCLK, HSMCLK, and SMCLK
175 * clock sources.
176 *
177 * To enable this bypass mode, set Boot.enableHFXT to true to enable the
178 * HFXT pins, and set Boot.bypassHFXT to true to disable the HFXT
179 * oscillator.
180 */
181 config Bool bypassHFXT = false;
182
183 /*!
184 * Watchdog disable configuration flag, default is true.
185 *
186 * Set to false to disable the disabling of the watchdog.
187 */
188 metaonly config Bool disableWatchdog = true;
189
190 /*!
191 * @_nodoc
192 * ======== registerFreqListener ========
193 * Register a module to be notified whenever the frequency changes.
194 *
195 * The registered module must have a function named 'fireFrequencyUpdate'
196 * which takes the new frequency as an argument.
197 */
198 function registerFreqListener();
199
200 internal:
201
202 203 204 205 206 207
208 Void init();
209
210 /*!
211 * computed cpu frequency based on clock settings
212 */
213 metaonly config UInt computedCpuFrequency;
214
215 };