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33 34 35 36
37 package ti.sysbios.family.arm.m3;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Assert;
43 import xdc.runtime.Error;
44 import xdc.runtime.Types;
45
46 import ti.sysbios.BIOS;
47 import ti.sysbios.interfaces.IHwi;
48
49 /*!
50 * ======== Hwi ========
51 * Cortex M3 Hardware Interrupt Manager
52 *
53 * The Cortex M3's Nested Vectored Interrupt Controller (NVIC)
54 * supports up to 256 interrupts/exceptions. In practice, most
55 * devices support much fewer (ie the Stellaris family of devices
56 * have only 80 total interrupts defined).
57 *
58 * SYS/BIOS Interrupt IDs or interrupt numbers correspond
59 * to an interrupt's position in the interrupt vector table.
60 *
61 * ID 0 corresponds to vector 0 which is used by the NVIC
62 * to hold the initial (reset) stack pointer value.
63 *
64 * ID 1 corresponds to vector 1 which is the reset vector (ie _c_int00)
65 *
66 * IDs 2-14 are hardwired to exceptions.
67 *
68 * ID 15 is the SysTick timer interrupt.
69 *
70 * ID's 16-255 are mapped to the NVIC's user interrupts 0-239
71 * which are tied to platform specific interrupt sources.
72 *
73 * @a(Zero Latency Interrupts)
74 * The M3 Hwi module supports "zero latency" interrupts.
75 * Interrupts configured with priority greater (in actual
76 * hardware priority, but lower in number) than
77 * {@link #disablePriority Hwi.disablePriority} are NOT
78 * disabled by Hwi_disable().
79 *
80 * Zero latency interrupts are distinguished from regular dispatched
81 * interrupts at create time by their priority being greater
82 * than Hwi.disablePriority.
83 *
84 * Note that since zero latency interrupts don't use the dispatcher,
85 * the {@link ti.sysbios.interfaces.IHwi#arg arg} parameter is not
86 * functional. Also note that due to the M3's native automatic
87 * stacking of saved-by-caller C context on the way to an ISR, zero
88 * latency interrupt handlers are implemented using regular C functions
89 * (ie no 'interrupt' keyword is required).
90 *
91 * @a(WARNING)
92 * Zero latency interrupts are NOT HANDLED by the SYS/BIOS
93 * interrupt dispatcher! Instead, they are vectored to directly.
94 * As such, and because they are NOT DISABLED BY Hwi_disable(),
95 * these interrupt handlers are SEVERELY RESTRICTED in terms of the
96 * SYS/BIOS APIs they can invoke and THREAD SAFETY MUST BE CAREFULLY
97 * CONSIDERED! See the descriptions of {@link #disable Hwi_disable()} and
98 * and {@link #disablePriority Hwi.disablePriority} for more details.
99 *
100 * @a(Interrupt Masking Options)
101 *
102 * The NVIC interrupt controller is designed for priority based
103 * interrupts.
104 *
105 * In this Hwi module, the {@link #maskSetting} instance configuration
106 * parameter is ignored.
107 * Effectively, only the {@link #MaskingOption_LOWER} is supported.
108 *
109 * @a(Interrupt Priorities)
110 *
111 * In general, the NVIC supports priority values of 0 thru 255.
112 *
113 * In practice, the number of priorities and their values are device
114 * dependent, and their nesting behaviors depend on the
115 * {@link #priGroup Hwi.priGroup} setting.
116 *
117 * For most TI MCU devices, 8 priorities are supported. A peculiarity
118 * of ARM's NVIC is that, although the priority field is an 8 bit value,
119 * the range of supported priority values are left-justified within this
120 * 8 bit field. Consequently, the 8 priority values are not 0 thru 7 as
121 * one might expect, but rather:
122 *
123 * @p(code)
124 * 0x00 // highest priority, non dispatched, Zero Latency priority
125 * 0x20 // highest dispatched interrupt priority
126 * 0x40
127 * 0x60
128 * 0x80
129 * 0xa0
130 * 0xc0
131 * 0xe0 // lowest dispatched interrupt priority, (default)
132 * @p
133 *
134 * Priority 0 is the highest priority and by default is
135 * reserved for zero latency interrupts
136 * (see {@link #disablePriority Hwi.disablePriority}).
137 *
138 * See the Cortex M3 architecture reference manual for details
139 * on the behavior of interrupt priorities and their relationship
140 * to the {@link #priGroup Hwi.priGroup} setting.
141 *
142 * @a(Interrupt Vector Tables)
143 * Tiva devices:
144 *
145 * By default, two vector tables are created for Tiva devices:
146 *
147 * A 16 entry boot vector table is placed at address 0x00000000 in
148 * FLASH.
149 *
150 * An 80 entry vector table is placed at address 0x20000000 in RAM.
151 *
152 * The FLASH boot vector table contains the reset vector and exception
153 * handler vectors used until the RAM based vector table is initialized.
154 *
155 * The RAM vector table contains the 16 exception vectors as well as all
156 * the 64 user interrupt vectors.
157 *
158 * During system startup, the NVIC Vector Table Offset Registor is
159 * intialized to point to this vector table after the table has been
160 * initialized.
161 *
162 * @a( )
163 * Dual M3 Core ('Ducati') devices:
164 *
165 * By default, Ducati core 0 places its runtime vector table at address
166 * 0x00000400 and core 1 places its runtime vector table at address
167 * 0x00000800.
168 *
169 * Additionally, a boot vector table is placed at address
170 * 0x00000000 which is shared by both cores.
171 *
172 * The boot reset vector function determines which core it is being
173 * executed on and jumps to the reset vector contained in its corresponding
174 * runtime vector table.
175 *
176 * The generation and placement of these vector tables is made
177 * automatically when the
178 * {@link ti.sysbios.family.arm.ducati.Core} module is used.
179 *
180 * Although STRONGLY discouraged, this default behavior can be overridden
181 * by explicitly setting the
182 * {@link #resetVectorAddress Hwi.resetVectorAddress} and
183 * {@link #vectorTableAddress Hwi.vectorTableAddress} config parameters.
184 *
185 * @a(Restrictions)
186 * When used within a dual M3 core (Ducati) arrangement, care must be
187 * taken when initializing this shared resource.
188 * The "Shared Resources" note provided
189 * in the {@link ti.sysbios.family.arm.ducati ducati} package discusses
190 * the management of the various hardware and software resources
191 * shared by the two M3 cores.
192 * @a
193 *
194 * @p(html)
195 * <h3> Calling Context </h3>
196 * <table border="1" cellpadding="3">
197 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
198 *
199 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
200 * <!-- -->
201 * <tr><td> {@link #clearInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
202 * <tr><td> {@link #create} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
203 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
204 * <tr><td> {@link #disableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
205 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
206 * <tr><td> {@link #enableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
207 * <tr><td> {@link #Params_init} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
208 * <tr><td> {@link #restore} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
209 * <tr><td> {@link #restoreInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
210 * <tr><td> {@link #construct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
211 * <tr><td> {@link #delete} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
212 * <tr><td> {@link #destruct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
213 * <tr><td> {@link #getHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
214 * <tr><td> {@link #setFunc} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
215 * <tr><td> {@link #setHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
216 * <tr><td colspan="6"> Definitions: <br />
217 * <ul>
218 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
219 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
220 * <li> <b>Task</b>: API is callable from a Task thread. </li>
221 * <li> <b>Main</b>: API is callable during any of these phases: </li>
222 * <ul>
223 * <li> In your module startup after this module is started (e.g. Hwi_Module_startupDone() returns TRUE). </li>
224 * <li> During xdc.runtime.Startup.lastFxns. </li>
225 * <li> During main().</li>
226 * <li> During BIOS.startupFxns.</li>
227 * </ul>
228 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
229 * <ul>
230 * <li> During xdc.runtime.Startup.firstFxns.</li>
231 * <li> In your module startup before this module is started (e.g. Hwi_Module_startupDone() returns FALSE).</li>
232 * </ul>
233 * </ul>
234 * </td></tr>
235 *
236 * </table>
237 * @p
238 */
239
240
241 @Template("./Hwi.xdt")
242 @ModuleStartup
243 @InstanceInitStatic
244
245 module Hwi inherits ti.sysbios.interfaces.IHwi
246 {
247
248
249 /*!
250 * The Cortex M3 NVIC supports up to 256 interrupts/exceptions.
251 *
252 * The actual number supported is device specific and provided by
253 * the catalog device specification.
254 */
255 config Int NUM_INTERRUPTS;
256
257 /*!
258 * The Cortex M3 NVIC supports up to 256 interrupt priorities.
259 *
260 * The actual number supported is device specific and provided by
261 * the catalog device specification.
262 */
263 config Int NUM_PRIORITIES;
264
265
266
267 /*! Hwi vector function type definition. */
268 typedef Void (*VectorFuncPtr)(void);
269
270 /*! Exception hook function type definition. */
271 typedef Void (*ExceptionHookFuncPtr)(ExcContext *);
272
273 /*! NVIC Configuration Control Register (CCR). */
274 struct CCR {
275 Bits8 STKALIGN; /*! Auto stack alignment in exception */
276 Bits8 BFHFNMIGN; /*! All faults ignore BUS Faults */
277 Bits8 DIV_0_TRP; /*! Trap on divide by zero */
278 Bits8 UNALIGN_TRP; /*! Trap on all unaligned accesses */
279 Bits8 USERSETMPEND; /*! Allow user to trigger interrupts */
280 Bits8 NONEBASETHRDENA; /*! Allow entering thread mode anytime */
281 };
282
283 /*! @_nodoc
284 * Nested Vectored Interrupt Controller.
285 */
286 struct NVIC {
287 UInt32 RES_00; /*! 0xE000E000 reserved */
288 UInt32 ICTR; /*! 0xE000E004 Interrupt Control Type */
289 UInt32 RES_08; /*! 0xE000E008 reserved */
290 UInt32 RES_0C; /*! 0xE000E00C reserved */
291 UInt32 STCSR; /*! 0xE000E010 SysTick Control & Status Register */
292 UInt32 STRVR; /*! 0xE000E014 SysTick Reload Value Register */
293 UInt32 STCVR; /*! 0xE000E018 SysTick Current Value Register */
294 UInt32 STCALIB; /*! 0xE000E01C SysTick Calibration Value Register */
295 UInt32 RES_20 [56]; /*! 0xE000E020-0xE000E0FC reserved */
296 UInt32 ISER [8]; /*! 0xE000E100-0xE000E11C Interrupt Set Enable Registers */
297 UInt32 RES_120 [24]; /*! 0xE000E120-0xE000E17C reserved */
298 UInt32 ICER [8]; /*! 0xE000E180-0xE000E19C Interrupt Clear Enable Registers */
299 UInt32 RES_1A0 [24]; /*! 0xE000E1A0-0xE000E1FC reserved */
300 UInt32 ISPR [8]; /*! 0xE000E200-0xE000E21C Interrupt Set Pending Registers */
301 UInt32 RES_220 [24]; /*! 0xE000E220-0xE000E7C reserved */
302 UInt32 ICPR [8]; /*! 0xE000E280-0xE000E29C Interrupt Clear Pending Registers */
303 UInt32 RES_2A0 [24]; /*! 0xE000E2A0-0xE000E2FC reserved */
304 UInt32 IABR [8]; /*! 0xE000E300-0xE000E31C Interrupt Active Bit Registers */
305 UInt32 RES_320 [56]; /*! 0xE000E320-0xE000E3FC reserved */
306 UInt8 IPR [240]; /*! 0xE000E400-0xE000E4EF Interrupt Priority Registers */
307 UInt32 RES_4F0 [516];/*! 0xE000E4F0-0xE000ECFC reserved */
308 UInt32 CPUIDBR; /*! 0xE000ED00 CPUID Base Register */
309 UInt32 ICSR; /*! 0xE000ED04 Interrupt Control State Register */
310 UInt32 VTOR; /*! 0xE000ED08 Vector Table Offset Register */
311 UInt32 AIRCR; /*! 0xE000ED0C Application Interrupt/Reset Control Register */
312 UInt32 SCR; /*! 0xE000ED10 System Control Register */
313 UInt32 CCR; /*! 0xE000ED14 Configuration Control Register */
314 UInt8 SHPR[12]; /*! 0xE000ED18 System Handlers 4-15 Priority Registers */
315 UInt32 SHCSR; /*! 0xE000ED24 System Handler Control & State Register */
316 UInt8 MMFSR; /*! 0xE000ED28 Memory Manage Fault Status Register */
317 UInt8 BFSR; /*! 0xE000ED29 Bus Fault Status Register */
318 UInt16 UFSR; /*! 0xE000ED2A Usage Fault Status Register */
319 UInt32 HFSR; /*! 0xE000ED2C Hard Fault Status Register */
320 UInt32 DFSR; /*! 0xE000ED30 Debug Fault Status Register */
321 UInt32 MMAR; /*! 0xE000ED34 Memory Manager Address Register */
322 UInt32 BFAR; /*! 0xE000ED38 Bus Fault Address Register */
323 UInt32 AFSR; /*! 0xE000ED3C Auxiliary Fault Status Register */
324 UInt32 PFR0; /*! 0xE000ED40 Processor Feature Register */
325 UInt32 PFR1; /*! 0xE000ED44 Processor Feature Register */
326 UInt32 DFR0; /*! 0xE000ED48 Debug Feature Register */
327 UInt32 AFR0; /*! 0xE000ED4C Auxiliary Feature Register */
328 UInt32 MMFR0; /*! 0xE000ED50 Memory Model Fault Register0 */
329 UInt32 MMFR1; /*! 0xE000ED54 Memory Model Fault Register1 */
330 UInt32 MMFR2; /*! 0xE000ED58 Memory Model Fault Register2 */
331 UInt32 MMFR3; /*! 0xE000ED5C Memory Model Fault Register3 */
332 UInt32 ISAR0; /*! 0xE000ED60 ISA Feature Register0 */
333 UInt32 ISAR1; /*! 0xE000ED64 ISA Feature Register1 */
334 UInt32 ISAR2; /*! 0xE000ED68 ISA Feature Register2 */
335 UInt32 ISAR3; /*! 0xE000ED6C ISA Feature Register3 */
336 UInt32 ISAR4; /*! 0xE000ED70 ISA Feature Register4 */
337 UInt32 RES_D74[5]; /*! 0xE000ED74-0xE000ED84 reserved */
338 UInt32 CPACR; /*! 0xE000ED88 Coprocessor Access Control Register */
339 UInt32 RES_D8C[93]; /*! 0xE000ED8C-0xE000EEFC reserved */
340 UInt32 STI; /*! 0xE000EF00 Software Trigger Interrupt Register */
341 UInt32 RES_F04[12]; /*! 0xE000EF04-0xE000EF30 reserved */
342 UInt32 FPCCR; /*! 0xE000EF34 FP Context Control Register */
343 UInt32 FPCAR; /*! 0xE000EF38 FP Context Address Register */
344 UInt32 FPDSCR; /*! 0xE000EF3C FP Default Status Control Register */
345 UInt32 MVFR0; /*! 0xE000EF40 Media & FP Feature Register0 */
346 UInt32 MVFR1; /*! 0xE000EF44 Media & FP Feature Register1 */
347 UInt32 RES_F48[34]; /*! 0xE000EF48-0xE000EFCC reserved */
348 UInt32 PID4; /*! 0xE000EFD0 Peripheral ID Register4 */
349 UInt32 PID5; /*! 0xE000EFD4 Peripheral ID Register5 */
350 UInt32 PID6; /*! 0xE000EFD8 Peripheral ID Register6 */
351 UInt32 PID7; /*! 0xE000EFDC Peripheral ID Register7 */
352 UInt32 PID0; /*! 0xE000EFE0 Peripheral ID Register0 */
353 UInt32 PID1; /*! 0xE000EFE4 Peripheral ID Register1 */
354 UInt32 PID2; /*! 0xE000EFE8 Peripheral ID Register2 */
355 UInt32 PID3; /*! 0xE000EFEC Peripheral ID Register3 */
356 UInt32 CID0; /*! 0xE000EFF0 Component ID Register0 */
357 UInt32 CID1; /*! 0xE000EFF4 Component ID Register1 */
358 UInt32 CID2; /*! 0xE000EFF8 Component ID Register2 */
359 UInt32 CID3; /*! 0xE000EFFC Component ID Register3 */
360 }
361
362 /*!
363 * Physical Nested Vectored Interrupt Controller Device.
364 * Short name is "Hwi_nvic"
365 * Long name is "ti_sysbios_family_arm_m3_Hwi_nvic"
366 */
367 extern volatile NVIC nvic;
368
369 /*!
370 * Virtual Nested Vectored Interrupt Controller structure
371 * written to by both cores for SMP.
372 * Short name is "Hwi_vnvic"
373 * Long name is "ti_sysbios_family_arm_m3_Hwi_vnvic"
374 */
375 extern volatile NVIC vnvic;
376
377 /*!
378 * Exception Context - Register contents at the time of an exception.
379 */
380 struct ExcContext {
381
382 BIOS.ThreadType threadType;
383
384 Ptr threadHandle;
385
386 Ptr threadStack;
387
388
389 SizeT threadStackSize;
390
391
392 Ptr r0;
393 Ptr r1;
394 Ptr r2;
395 Ptr r3;
396 Ptr r4;
397 Ptr r5;
398 Ptr r6;
399 Ptr r7;
400 Ptr r8;
401 Ptr r9;
402 Ptr r10;
403 Ptr r11;
404 Ptr r12;
405 Ptr sp;
406 Ptr lr;
407 Ptr pc;
408 Ptr psr;
409
410
411 Ptr ICSR;
412 Ptr MMFSR;
413 Ptr BFSR;
414 Ptr UFSR;
415 Ptr HFSR;
416 Ptr DFSR;
417 Ptr MMAR;
418 Ptr BFAR;
419 Ptr AFSR;
420 }
421
422 struct Struct2__ {
423 Ptr fxns;
424 UArg arg;
425 FuncPtr fxn;
426 Irp irp;
427 UInt8 priority;
428 Int16 intNum;
429 Ptr hookEnv;
430 Types.CordAddr name;
431 };
432
433 typedef Struct2__ Struct2;
434
435 /*! @_nodoc */
436 metaonly struct BasicView {
437 Ptr halHwiHandle;
438 String label;
439 String type;
440 Int intNum;
441 Int priority;
442 Int group;
443 Int subPriority;
444 String fxn;
445 UArg arg;
446 };
447
448 /*! @_nodoc */
449 metaonly struct DetailedView {
450 Ptr halHwiHandle;
451 String label;
452 String type;
453 Int intNum;
454 Int priority;
455 Int group;
456 Int subPriority;
457 String fxn;
458 UArg arg;
459 Ptr irp;
460 String status;
461 Int coreId;
462 };
463
464 /*! @_nodoc */
465 metaonly struct ModuleView {
466 String options[4];
467 String activeInterrupt;
468 String pendingInterrupt;
469 String exception;
470 String hwiStackPeak;
471 SizeT hwiStackSize;
472 Ptr hwiStackBase;
473 };
474
475 /*! @_nodoc */
476 @Facet
477 metaonly config ViewInfo.Instance rovViewInfo =
478 ViewInfo.create({
479 viewMap: [
480 ['Basic',
481 {
482 type: ViewInfo.INSTANCE,
483 viewInitFxn: 'viewInitBasic',
484 structName: 'BasicView'
485 }
486 ],
487 ['Detailed',
488 {
489 type: ViewInfo.INSTANCE,
490 viewInitFxn: 'viewInitDetailed',
491 structName: 'DetailedView'
492 }
493 ],
494 ['Module',
495 {
496 type: ViewInfo.MODULE,
497 viewInitFxn: 'viewInitModule',
498 structName: 'ModuleView'
499 }
500 ],
501 ['Exception',
502 {
503 type: ViewInfo.TREE,
504 viewInitFxn: 'viewInitException',
505 structName: 'ExcContext'
506 }
507 ]
508 ]
509 });
510
511
512
513
514
515 /*!
516 * Issued just prior to Hwi function invocation (with interrupts disabled)
517 */
518 config Log.Event LM_begin = {
519 mask: Diags.USER1 | Diags.USER2,
520 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
521 };
522
523 /*!
524 * Issued just after return from Hwi function (with interrupts disabled)
525 */
526 config Log.Event LD_end = {
527 mask: Diags.USER2,
528 msg: "LD_end: hwi: 0x%x"
529 };
530
531
532
533 /*! Assert when bad maskSetting parameter provided */
534 config Assert.Id A_unsupportedMaskingOption = {
535 msg: "A_unsupportedMaskingOption: unsupported maskSetting."
536 };
537
538
539
540 /*!
541 * Error raised when Hwi is already defined
542 */
543 config Error.Id E_alreadyDefined = {
544 msg: "E_alreadyDefined: Hwi already defined: intr# %d"
545 };
546
547 /*!
548 * Error raised when the number of interrupts being created
549 * exceeds the number supported.
550 */
551 config Error.Id E_hwiLimitExceeded = {
552 msg: "E_hwiLimitExceeded: Too many interrupts defined"
553 };
554
555 /*!
556 * Error raised when an exception occurs
557 */
558 config Error.Id E_exception = {
559 msg: "E_exception: id = %d, pc = %08x.\nTo see more exception detail, set ti.sysbios.family.arm.m3.Hwi.enableException = true or,\nexamine the Exception view for the ti.sysbios.family.arm.m3.Hwi module using ROV."
560 };
561
562 /*!
563 * Error raised when an uninitialized interrupt occurs
564 */
565 config Error.Id E_noIsr = {
566 msg: "E_noIsr: id = %d, pc = %08x"
567 };
568
569 /*!
570 * Error raised when NMI exception occurs
571 */
572 config Error.Id E_NMI = {
573 msg: "E_NMI: %s"
574 };
575
576 /*!
577 * Error raised when hard fault exception occurs
578 */
579 config Error.Id E_hardFault = {
580 msg: "E_hardFault: %s"
581 };
582
583 /*!
584 * Error raised when memory fault exception occurs
585 */
586 config Error.Id E_memFault = {
587 msg: "E_memFault: %s, address: %08x"
588 };
589
590 /*!
591 * Error raised when bus fault exception occurs
592 */
593 config Error.Id E_busFault = {
594 msg: "E_busFault: %s, address: %08x"
595 };
596
597 /*!
598 * Error raised when usage fault exception occurs
599 */
600 config Error.Id E_usageFault = {
601 msg: "E_usageFault: %s"
602 };
603
604 /*!
605 * Error raised when svCall exception occurs
606 */
607 config Error.Id E_svCall = {
608 msg: "E_svCall: svNum = %d"
609 };
610
611 /*!
612 * Error raised when debugMon exception occurs
613 */
614 config Error.Id E_debugMon = {
615 msg: "E_debugMon: %s"
616 };
617
618 /*!
619 * Error raised when reserved exception occurs
620 */
621 config Error.Id E_reserved = {
622 msg: "E_reserved: %s %d"
623 };
624
625
626
627 /*!
628 * Size (in number of interrupts) of the table used by the interrupt
629 * dispatcher to locate the corresponding Hwi object. By default,
630 * Hwi.dispatchTableSize will be internally set
631 * to the number of interrupts supported by the device.
632 *
633 * When the Hwi dispatch table size is equal to the number of interrupts
634 * supported {@link #NUM_INTERRUPTS} by the device, a linear-indexed
635 * dispatch table mechanism is used that will consume 4 bytes of RAM
636 * for each interrupt supported.
637 *
638 * If the dispatch table size is set to a number less than the number
639 * of interrupts supported by the device, then a non linear-indexed
640 * dispatch table mechanism is employed that uses 12 bytes of RAM for
641 * each interrupt supported.
642 *
643 * Consequently, for applications that use less than 1/3 of the total
644 * number of interrupts supported by the device, setting this parameter
645 * to the number of interrupts ACTUALLY USED will result in less RAM
646 * memory being used than otherwise.
647 *
648 * For applications that use very few interrupts, this can be a significant RAM memory savings.</p>
649 */
650 metaonly config UInt dispatchTableSize;
651
652 /*!
653 * Location of the Runtime Interrupt Vector Table.
654 * Default is device dependent.
655 *
656 * This parameter allows the user to override the default placement
657 * of the runtime interrupt vector table.
658 * The NVIC's Vector Table Offset
659 * Register (VTOR) is also programmed to this value.
660 *
661 * Some systems require the runtime vector table to be placed at
662 * an address
663 * other than 0 but still need a copy of the two M3 boot vectors
664 * (SP and reset PC), located there. To achieve this, a separate
665 * parameter {@link #resetVectorAdress} is provided. If the
666 * resetVectorAddress has a different value then the vectorTableAddress
667 * then a separate vector table is generated and placed at that
668 * address.
669 *
670 * The vector table must be placed at an address at or lower than
671 * 0x3FFFFC00 and must be aligned on an even 64 word boundary.
672 */
673 metaonly config Ptr vectorTableAddress = 0x00000000;
674
675 /*!
676 * Reset vector table address. Default is 0x00000000.
677 *
678 * This parameter is the address of the vector table used
679 * at system reset time. Typically this is placed at 0x00000000.
680 *
681 * If the Hwi.resetVectorAddress has a different value than
682 * the {@link #vectorTableAddress Hwi.vectorTableAddress}
683 * then two vector tables are generated, one at the Hwi.resetVectorAddress
684 * and another at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
685 *
686 * After the initial boot code has been executed at startup, the NVIC's
687 * Vector Table Offset Register will be programmed to point to the
688 * vector table at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
689 *
690 * is created and placed in the ".resetVecs" section.
691 */
692 metaonly config Ptr resetVectorAddress = 0x00000000;
693
694 /*! Reset Handler. Default is c_int00 */
695 metaonly config VectorFuncPtr resetFunc;
696
697 /*! NMI Handler. Default is set to an internal exception handler */
698 metaonly config VectorFuncPtr nmiFunc;
699
700 /*! Hard Fault Handler. Default is set to an internal exception handler */
701 metaonly config VectorFuncPtr hardFaultFunc;
702
703 /*! Hard Mem Handler. Default is set to an internal exception handler */
704 metaonly config VectorFuncPtr memFaultFunc;
705
706 /*! Bus Fault Handler. Default is set to an internal exception handler */
707 metaonly config VectorFuncPtr busFaultFunc;
708
709 /*! Usage Fault Handler. Default is set to an internal exception handler */
710 metaonly config VectorFuncPtr usageFaultFunc;
711
712 /*! SVCall Handler. Default is set to an internal exception handler */
713 metaonly config VectorFuncPtr svCallFunc;
714
715 /*! Debug Mon Handler. Default is set to an internal exception handler */
716 metaonly config VectorFuncPtr debugMonFunc;
717
718 /*! Reserved Exception Handler. Default is set to an internal exception handler */
719 metaonly config VectorFuncPtr reservedFunc;
720
721 /*! Uninitialized ISR Handler. Default is set to an internal exception handler */
722 config VectorFuncPtr nullIsrFunc;
723
724 /*! Hwi exception handler function type definition. */
725 typedef Void (*ExcHandlerFuncPtr)(UInt *, UInt);
726
727 /*!
728 * Exception handler function pointer.
729 *
730 * The default is determined by the value of Hwi.enableException.
731 *
732 * If the user does NOT set this parameter, then the following default
733 * behavior is followed:
734 *
735 * If Hwi.enableException is true, then the internal 'Hwi_excHandlerMax'
736 * function is used. This exception handler saves the exception context
737 * then does a complete exception decode and dump to the console, then
738 * raises an Error. The exception context can be viewed within CCS
739 * in the ROV Hwi module's Exception view.
740 *
741 * If Hwi.enableException is false, then the internal 'Hwi_excHandlerMin'
742 * function is used. This exception handler saves the exception context
743 * then raises an Error. The exception context can be viewed within CCS
744 * in the ROV Hwi module's Exception view.
745 *
746 * If the user sets this parameter to their own function, then the user's
747 * function will be invoked with the following arguments:
748 *
749 * Void myExceptionHandler(UInt *excStack, UInt lr);
750 *
751 * Where 'excStack' is the address of the stack containing the
752 * register context at the time of the exception, and 'lr' is the
753 * link register value when the low-level-assembly-coded exception
754 * handler was vectored to.
755 *
756 * If this parameter is set to 'null', then an infinite while loop is
757 * entered when an exception occurs. This setting minimizes code and
758 * data footprint but provides no automatic exception decoding.
759 */
760 config ExcHandlerFuncPtr excHandlerFunc = excHandlerMax;
761
762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788
789 metaonly config UInt8 intAffinity[];
790
791 /*!
792 * Enable full exception decoding
793 *
794 * When this is enabled, the exception handler will fully
795 * decode an exception and dump the registers to the
796 * system console.
797 */
798 metaonly config Bool enableException = true;
799
800 /*!
801 * User Exception Context Buffer Address
802 *
803 * By default, when an exception occurs, an {@link #ExcContext}
804 * structure is allocated on the ISR stack and filled in within the
805 * exception handler.
806 *
807 * If {@link #excContextBuffer} is initialized by the user, the
808 * {@link #ExcContext} structure will be placed at that address instead.
809 *
810 * The buffer must be large enough to contain an {@link #ExcContext}
811 * structure.
812 */
813 metaonly config Ptr excContextBuffer;
814 metaonly config Ptr excContextBuffers[];
815
816 /*!
817 * User Exception Stack Buffer Address
818 *
819 * By default, when an exception occurs, a pointer to the base address
820 * of the stack being used by the thread causing the exception is placed
821 *
822 * If {@link #excStackBuffer} is initialized by the user, the
823 * stack contents of the thread causing the exception will be
824 * copied to that address instead.
825 *
826 * The buffer must be large enough to contain the largest task stack
827 * or ISR stack defined in the application.
828 */
829 metaonly config Ptr excStackBuffer;
830 metaonly config Ptr excStackBuffers[];
831
832
833 /*!
834 * User Exception hook function.
835 *
836 * Called just after the exception context has been initialized.
837 *
838 * This function will be run on the ISR stack.
839 *
840 * This function must run to completion.
841 *
842 * It is called without any Task or Swi scheduling protection
843 * and therefore can not call any functions that may cause a Swi or Task
844 * scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
845 */
846 config ExceptionHookFuncPtr excHookFunc = null;
847 config ExceptionHookFuncPtr excHookFuncs[];
848
849 /*!
850 * NVIC CCR register settings
851 *
852 * These setting are written to Hwi_nvic.CCR at startup time.
853 *
854 * See the Cortex M3 architecture reference manual for details
855 * on the meanings of these parameters.
856 */
857 metaonly config CCR nvicCCR = {
858 STKALIGN: 1,
859 BFHFNMIGN: 0,
860 DIV_0_TRP: 0,
861 UNALIGN_TRP: 0,
862 USERSETMPEND: 0,
863 NONEBASETHRDENA: 0
864 };
865
866 /*!
867 * The priority that BASEPRI is set to by Hwi_disable().
868 *
869 * All interrupts configured with equal or less priority (equal or
870 * higher number) than disablePriority are disabled by
871 * {@link #disable Hwi_disable}.
872 * Interrupts configured with higher priority (smaller number) than
873 * Hwi.disablePriority are non-maskable (ie zero-latency).
874 *
875 * The default setting is the second highest interrupt priority
876 * defined for the device (typically '0x20' for devices
877 * which support 8 priority values).
878 * This results in priority 0 (and all
879 * other values in the same priority group, ie 0x00 thru 0x1f)
880 * being the zero-latency, non-maskable interrupt priority.
881 * All other priorities are disabled with Hwi_disable().
882 */
883 config UInt disablePriority;
884
885 /*!
886 * The PRIGROUP setting. Default is 0.
887 *
888 * This value will be written to the PRIGROUP field
889 * within the NVIC's Application Interrupt and Reset Control
890 * Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
891 * values are interpreted by the hardware.
892 *
893 * Valid settings are 0-7.
894 *
895 * The default setting of 0 causes bits 7-1 of an interrupt's
896 * priority value to be used as pre-emption priority, while bit 0
897 * is used to determine which of two simultaneous interrupts with
898 * the same pre-emption priority will be serviced first.
899 *
900 * For most TI MCU devices, this means that each of the 8 supported
901 * priority values are unique pre-emption priorities and are not
902 * subdivided into priority groups.
903 */
904 config UInt priGroup = 0;
905
906
907
908 /*!
909 * ======== construct2 ========
910 * Construct a Hwi object
911 *
912 * Hwi_construct2 constructs a Hwi object. This function is identical
913 * to Hwi_construct(), but does not take an Error_Block parameter, and
914 * returns a Hwi_Handle.
915 *
916 * The following C code sets Hwi parameters and
917 * constructs a Hwi object:
918 *
919 * @p(code)
920 *
921 * Hwi_Struct2 hwiStruct2;
922 * Hwi_Handle hwi;
923 *
924 * Void main()
925 * {
926 * Hwi_Params hwiParams;
927 *
928 * Hwi_Params_init(&hwiParams);
929 * hwiParams.arg = (UArg)arg;
930 * hwiParams.priority = intPriority;
931 *
932 * hwi = Hwi_construct2(&hwiStruct2, intNum, hwiFxn, &hwiParams);
933 * if (hwi == NULL) {
934 * // Failure
935 * }
936 *
937 * BIOS_start();
938 * }
939 * @p
940 *
941 * @param(hwi) Pointer to Hwi_Struct2 object.
942 * @param(intNum) Interrupt priority
943 * @param(hwiFxn) Hwi Function
944 * @param(prms) Pointer to Hwi_Params structure
945 *
946 * @b(returns) A Hwi handle
947 */
948 Handle construct2(Struct2 *hwi, Int intNum, FuncPtr hwiFxn,
949 const Params *prms);
950
951 /*!
952 * ======== disable ========
953 * Disable all non zero-latency interrupts
954 *
955 * Hwi_disable disables all non zero-latency hardware interrupts and
956 * returns an
957 * opaque key indicating whether interrupts were globally enabled or
958 * disabled on entry to Hwi_disable().
959 * The actual value of the key is target/device specific and is meant
960 * to be passed to Hwi_restore().
961 *
962 * Call Hwi_disable before a portion of a function that needs
963 * to run without interruption. When critical processing is complete, call
964 * Hwi_restore or Hwi_enable to reenable hardware interrupts.
965 *
966 * Servicing of interrupts that occur while interrupts are disabled is
967 * postponed until interrupts are reenabled. However, if the same type
968 * of interrupt occurs several times while interrupts are disabled,
969 * the interrupt's function is executed only once when interrupts are
970 * reenabled.
971 *
972 * A context switch can occur when calling Hwi_enable or Hwi_restore if
973 * an enabled interrupt occurred while interrupts are disabled.
974 *
975 * Hwi_disable may be called from main(). However, since Hwi interrupts
976 * are already disabled in main(), such a call has no effect.
977 *
978 * @a(Implementation Note)
979 * In order to support zero latency interrupts, rather
980 * than setting PRIMASK (which would globally disable all NVIC
981 * interrupts), Hwi_disable() instead writes the value of
982 * {@link #disablePriority Hwi.disablePriority}
983 * to the BASEPRI register. In doing so, all interrupts of equal or
984 * lower priority than Hwi.disablePriority are disabled.
985 *
986 * @a(constraints)
987 * If a Task switching API such as
988 * {@link ti.sysbios.knl.Semaphore#pend Semaphore_pend()},
989 * {@link ti.sysbios.knl.Semaphore#post Semaphore_post()},
990 * {@link ti.sysbios.knl.Task#sleep Task_sleep()}, or
991 * {@link ti.sysbios.knl.Task#yield Task_yield()}
992 * is invoked which results in a context switch while
993 * interrupts are disabled, an embedded call to
994 * {@link #enable Hwi_enable} occurs
995 * on the way to the new thread context which unconditionally re-enables
996 * interrupts. Interrupts will remain enabled until a subsequent
997 * {@link #disable Hwi_disable}
998 * invocation.
999 *
1000 * Swis always run with interrupts enabled.
1001 * See {@link ti.sysbios.knl.Swi#post Swi_post()} for a discussion Swis and
1002 * interrupts.
1003 *
1004 * @b(returns) opaque key for use by Hwi_restore()
1005 */
1006 @Macro
1007 override UInt disable();
1008
1009 /*!
1010 * ======== enable ========
1011 */
1012 @Macro
1013 override UInt enable();
1014
1015 /*!
1016 * ======== restore ========
1017 */
1018 @Macro
1019 override Void restore(UInt key);
1020
1021 /*!
1022 * @_nodoc
1023 * ======== disableFxn ========
1024 * function call implementation
1025 */
1026 UInt disableFxn();
1027
1028 /*!
1029 * @_nodoc
1030 * ======== enableFxn ========
1031 * function call implementation
1032 */
1033 UInt enableFxn();
1034
1035 /*!
1036 * @_nodoc
1037 * ======== restoreFxn ========
1038 * function call implementation
1039 */
1040 Void restoreFxn(UInt key);
1041
1042 /*!
1043 * ======== inUseMeta ========
1044 * @_nodoc
1045 * Check for Hwi already in use.
1046 * For internal SYS/BIOS use only.
1047 * Should be called prior to any internal Hwi.create().
1048 *
1049 * @param(intNum) interrupt number
1050 */
1051 metaonly Bool inUseMeta(UInt intNum);
1052
1053 /*!
1054 * ======== plug ========
1055 * Plug a non dispatched interrupt vector with an ISR address.
1056 *
1057 * Used internally by Hwi_create() and Hwi_construct().
1058 *
1059 * This API is provided for external use primarily to allow users
1060 * to plug the NMI vector (interrupt #2) at runtime.
1061 *
1062 * @a(Note)
1063 * Interrupt vectors plugged using Hwi_plug() are NOT managed by
1064 * the Hwi interrupt dispatcher. Consequently, it is not safe to
1065 * call SYS/BIOS APIs from within these ISRs.
1066 *
1067 * @param(intNum) interrupt number
1068 * @param(fxn) pointer to ISR function
1069 */
1070 Void plug(UInt intNum, Void *fxn);
1071
1072 /*!
1073 * ======== getHandle ========
1074 * Returns Hwi_handle associated with intNum
1075 *
1076 * @param(intNum) interrupt number
1077 */
1078 Handle getHandle(UInt intNum);
1079
1080 /*!
1081 * ======== setPriority ========
1082 * Set an interrupt's relative priority.
1083 *
1084 * Valid priorities are 0 - 255. 0 is highest priority.
1085 *
1086 * @a(WARNING)
1087 * Setting the priority of a dispatched Hwi to a value higher
1088 * than {@link #disablePriority Hwi.disablePriority} will make
1089 * it become non-maskable by {@link #disable Hwi_disable()}.
1090 * The behavior of your application after that will be
1091 * unpredictable and will likely yield catastrophic results!
1092 *
1093 * @param(intNum) ID of interrupt
1094 * @param(priority) priority
1095 */
1096 Void setPriority(UInt intNum, UInt priority);
1097
1098 /*!
1099 * ======== excSetBuffers ========
1100 * Set the exception context and stack buffer pointers
1101 *
1102 * @param(excContextBuffer) Address to place ExcContext
1103 * @param(excStackBuffer) Address to place ExcStack
1104 */
1105 Void excSetBuffers(Ptr excContextBuffer, Ptr excStackBuffer);
1106
1107 /*!
1108 * @_nodoc
1109 * ======== initNVIC ========
1110 * initialize everything but leave ints disabled
1111 */
1112 Void initNVIC();
1113
1114 /*!
1115 * @_nodoc
1116 * ======== initStacks ========
1117 * set up M3 split stacks
1118 */
1119 Void initStacks(Ptr hwiStack);
1120
1121 /*!
1122 * @_nodoc
1123 * ======== flushVnvic ========
1124 * Reconfigure a dispatched interrupt.
1125 *
1126 * Called by the internal function "Hwi_updateNvic()".
1127 *
1128 * This is a public API because it is also called by "Core_hwiFunc()".
1129 */
1130 Void flushVnvic();
1131
1132 instance:
1133
1134 /*!
1135 * Interrupt priority.
1136 * The default is 255 which is the lowest priority.
1137 *
1138 * Priority 0 is the highest priority and by default is
1139 * reserved for zero latency interrupts
1140 * (see {@link #disablePriority}).
1141 *
1142 * Valid priorities values are device dependent and their
1143 * nesting behaviors depend on the {@link #priGroup} setting.
1144 *
1145 * See the Cortex M3 architecture reference manual for details
1146 * on the meanings of these parameters.
1147 */
1148 override config Int priority = 255;
1149
1150 /*!
1151 * Interrupt Masking Option. Only MaskingOption_LOWER is supported.
1152 *
1153 * The NVIC interrupt controller is designed for priority based
1154 * interrupts. No support is provided for anything but
1155 * Hwi.MaskingOption_LOWER.
1156 */
1157 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
1158
1159 /*!
1160 * Use the interrupt dispatcher with this interrupt. Default is true.
1161 *
1162 * If set to false, the interrupt dispatcher is NOT used. Instead,
1163 * the configured Hwi function address is placed directly in the
1164 * vector table, which results in the dispatcher being bypassed.
1165 *
1166 * @a(Warning)
1167 * Interrupts configured to bupass the dispatcher are not allowed
1168 * to call ANY SYS/BIOS APIs that effect thread scheduling. Examples
1169 * of API that should no be invoked are:
1170 *
1171 * @p(dlist)
1172 * - Swi_post(),
1173 * - Semaphore_post(),
1174 * - Event_post(),
1175 * - Task_yield()
1176 * @p
1177 *
1178 * Additionally, although the signature for a non-dispatched interrupt
1179 * function is the same as that for a dispatched interrupt
1180 * (see {@link #FuncPtr}), no argument is actually passed
1181 * to the non-dispatched ISR handler.
1182 */
1183 config Bool useDispatcher = true;
1184
1185 /*!
1186 * ======== reconfig ========
1187 * Reconfigure a dispatched interrupt.
1188 */
1189 Void reconfig(FuncPtr fxn, const Params *params);
1190
1191 internal:
1192
1193 /*!
1194 * If Hwi.dispatchTableSize is initialized by the user then
1195 * Hwi.numSparseInterrupts is set to the value of Hwi.dispatchTableSize
1196 *
1197 * If Hwi.dispatchTableSize is NOT set by the user, the normal
1198 * intNum-indexed Hwi dispatchTable mechanism is used by
1199 * the dispatcher to find the corresponding Hwi object.
1200 *
1201 * If Hwi.dispatchTableSize is set by the user, then a
1202 * RAM-based fixed sized interrupt jump table is generated
1203 * that contains a repeating pattern of the following 3 word
1204 * assembly code snippets:
1205 *
1206 * hwiX: ldr r3, hwiObjectX
1207 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1208 * hwiObjectX: .word 0
1209 * hwiY: ldr r3, hwiObjectY
1210 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1211 * hwiObjectY: .word 0
1212 * ...
1213 *
1214 * Each dispatched interrupt vector is then initialized to point
1215 * to one of these tuples, and the address of the corresponding Hwi
1216 * object is written into the hwiObjectX field.
1217 *
1218 * The low level assembly code in Hwi_dispatch__I preserves the
1219 * value of r3 when it calls Hwi_dispatchC(), which results in
1220 * the Hwi object being passed as the arg3.
1221 *
1222 * Depending on the boolean value of Hwi_numSparseInterrupts, the
1223 * dispatcher either uses the value passed in arg3 as the
1224 * Hwi object, or uses intNum to index into the standard
1225 * dispatchTable to fetch the Hwi object.
1226 */
1227 config UInt numSparseInterrupts = 0;
1228
1229 1230 1231 1232
1233 metaonly config Bool isTiva = false;
1234
1235 1236 1237 1238 1239 1240 1241 1242 1243
1244 metaonly config Bool enableWA1_1 = false;
1245
1246 1247 1248 1249 1250 1251
1252 config UInt (*swiDisable)();
1253 config Void (*swiRestoreHwi)(UInt);
1254 config UInt (*taskDisable)();
1255 config Void (*taskRestoreHwi)(UInt);
1256
1257
1258 config UInt32 ccr;
1259
1260 /*!
1261 * const array to hold all HookSet objects.
1262 */
1263 config HookSet hooks[length] = [];
1264
1265 1266 1267 1268
1269 Int postInit(Object *hwi, Error.Block *eb);
1270
1271 /*!
1272 * ======== updateNvic ========
1273 * Internal SMP function to cause the virtual NVIC to be flushed to the
1274 * actual NVIC.
1275 *
1276 * This function is called by the various user APIs that manipulate
1277 * individual NVIC register bits
1278 * (ie Hwi_enable/disable/restore/clearInterrupt())
1279 *
1280 * If the current core is the owner of "intNum", flushVnvic() is called
1281 * immediately.
1282 *
1283 * Otherwise an intercore interrupt is generated to force the other core
1284 * to perform the flushVnvic().
1285 *
1286 */
1287 Void updateNvic(UInt intNum);
1288
1289 /*!
1290 * ======== excHandlerAsm ========
1291 * asm code exception handler
1292 */
1293 Void excHandlerAsm();
1294
1295 /*!
1296 * ======== excHandler ========
1297 * exception Handler routes to
1298 * either min, max, or spin exception handler
1299 */
1300 Void excHandler(UInt *excStack, UInt lr);
1301
1302 /*!
1303 * ======== excHandlerMin ========
1304 * Minimal Exception Handler
1305 */
1306 Void excHandlerMin(UInt *excStack, UInt lr);
1307
1308 /*!
1309 * ======== excHandlerMax ========
1310 * Full Featured Exception Handler
1311 */
1312 Void excHandlerMax(UInt *excStack, UInt lr);
1313
1314 /*!
1315 * ======== excFillContext ========
1316 */
1317 Void excFillContext(UInt *excStack);
1318
1319 /*!
1320 * ======== excNmi ========
1321 */
1322 Void excNmi(UInt *excStack);
1323
1324 /*!
1325 * ======== excHardFault ========
1326 */
1327 Void excHardFault(UInt *excStack);
1328
1329 /*!
1330 * ======== excMemFault ========
1331 */
1332 Void excMemFault(UInt *excStack);
1333
1334 /*!
1335 * ======== excBusFault ========
1336 */
1337 Void excBusFault(UInt *excStack);
1338
1339 /*!
1340 * ======== excUsageFault ========
1341 */
1342 Void excUsageFault(UInt *excStack);
1343
1344 /*!
1345 * ======== excSvCall ========
1346 */
1347 Void excSvCall(UInt *excStack);
1348
1349 /*!
1350 * ======== excDebugMon ========
1351 */
1352 Void excDebugMon(UInt *excStack);
1353
1354 /*!
1355 * ======== excReserved ========
1356 */
1357 Void excReserved(UInt *excStack, UInt excNum);
1358
1359 /*!
1360 * ======== excNoIsr ========
1361 */
1362 Void excNoIsr(UInt *excStack, UInt excNum);
1363
1364 /*!
1365 * ======== excDumpRegs ========
1366 */
1367 Void excDumpRegs(UInt lr);
1368
1369 /*!
1370 * ======== pendSV ========
1371 * Used by dispatcher
1372 */
1373 Void pendSV();
1374
1375 /*! Hwi vector function type definition. */
1376 typedef Void (*HandlerFuncPtr)(Handle, UInt);
1377
1378
1379 Void dispatch();
1380
1381 1382 1383 1384 1385 1386
1387 Void romInitNVIC();
1388
1389 1390 1391 1392
1393 UInt dispatchC(Irp irp, UInt32 dummy1, UInt32 dummy2, Object *hwi);
1394
1395
1396 Void doSwiRestore(UInt tskKey);
1397
1398
1399 Void doTaskRestore(UInt tskKey);
1400
1401 /*! Meta World Only Hwi Configuration Object. */
1402 metaonly struct InterruptObj {
1403 String name;
1404 Bool used;
1405 Bool useDispatcher;
1406 UInt priority;
1407 FuncPtr fxn;
1408 Handle hwi;
1409 };
1410
1411 /*!
1412 * Meta-only array of interrupt objects.
1413 * This meta-only array of Hwi config objects is initialized
1414 * in Hwi.xs:module$meta$init().
1415 */
1416 metaonly config InterruptObj interrupt[];
1417
1418 struct Instance_State {
1419 UArg arg;
1420 FuncPtr fxn;
1421 Irp irp;
1422
1423 UInt8 priority;
1424 Int16 intNum;
1425
1426
1427 Ptr hookEnv[];
1428 };
1429
1430 struct Module_State {
1431 Char *taskSP;
1432
1433 Bool excActive[];
1434 ExcContext *excContext[];
1435 Ptr excStack[];
1436 Ptr isrStack;
1437 Ptr isrStackBase;
1438 Ptr isrStackSize;
1439 Ptr vectorTableBase;
1440 UInt swiTaskKeys;
1441 Ptr dispatchTable;
1442 volatile Bool vnvicFlushRequired;
1443
1444 UInt8 intAffinity[];
1445 UInt32 intAffinityMasks[][];
1446 };
1447 }