module ti.sysbios.family.arm.arm9.Cache

ARM Cache Module

This module manages the data and instruction caches on ARM processors. It provides a list of functions that perform cache operations. The functions operate on a per cache line except for the 'All' functions which operate on the entire cache specified. Any Address that is not aligned to a cache line gets rounded down to the address of the nearest cache line. [ more ... ]
C synopsis target-domain sourced in ti/sysbios/family/arm/arm9/Cache.xdc
#include <ti/sysbios/family/arm/arm9/Cache.h>
Functions
Void 
Void 
Functions common to all ICache modules
Void 
Void 
Void 
Void 
Void 
Cache_wb// Writes back a range of memory from all cache(s)(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
Void 
Void 
Void 
Functions common to all target modules
Defines
#define
#define
Typedefs
typedef enum
Constants
extern const Bool 
 
DETAILS
This module manages the data and instruction caches on ARM processors. It provides a list of functions that perform cache operations. The functions operate on a per cache line except for the 'All' functions which operate on the entire cache specified. Any Address that is not aligned to a cache line gets rounded down to the address of the nearest cache line.
The L1 data and program caches are enabled by default early during the startup sequence (prior to any Module_startup()s). Data caching requires the MMU to be enabled and the cacheable attribute of the section/page descriptor for a corresponding memory region to be enabled. Program caching does not require the MMU to be enabled and therefore occurs when the L1 program cache is enabled.
Note: See the ti.sysbios.family.arm.arm9.Mmu module for information about the MMU.
Unconstrained Functions All functions

Calling Context

Function Hwi Swi Task Main Startup
disable Y Y Y Y Y
enable Y Y Y Y Y
inv Y Y Y Y Y
invL1dAll Y Y Y Y Y
invL1pAll Y Y Y Y Y
wait Y Y Y Y Y
wb Y Y Y Y Y
wbInv Y Y Y Y Y
wbInvL1dAll Y Y Y Y Y
wbL1dAll Y Y Y Y Y
Definitions:
  • Hwi: API is callable from a Hwi thread.
  • Swi: API is callable from a Swi thread.
  • Task: API is callable from a Task thread.
  • Main: API is callable during any of these phases:
    • In your module startup after this module is started (e.g. Cache_Module_startupDone() returns TRUE).
    • During xdc.runtime.Startup.lastFxns.
    • During main().
    • During BIOS.startupFxns.
  • Startup: API is callable during any of these phases:
    • During xdc.runtime.Startup.firstFxns.
    • In your module startup before this module is started (e.g. Cache_Module_startupDone() returns FALSE).
 
const Cache_sizeL1dCacheLine

Size of L1 data cache Line

C synopsis target-domain
#define Cache_sizeL1dCacheLine (UInt)32
 
 
const Cache_sizeL1pCacheLine

Size of L1 program cache Line

C synopsis target-domain
#define Cache_sizeL1pCacheLine (UInt)32
 
 
enum Cache_Type

Lists of bitmask cache types

C synopsis target-domain
typedef enum Cache_Type {
    Cache_Type_L1P,
    // Level 1 Program cache
    Cache_Type_L1D,
    // Level 1 Data cache
    Cache_Type_L1,
    // Level 1 caches
    Cache_Type_L2P,
    // Level 2 Program cache
    Cache_Type_L2D,
    // Level 2 Data cache
    Cache_Type_L2,
    // Level 2 caches
    Cache_Type_ALLP,
    // All Program caches
    Cache_Type_ALLD,
    // All Data caches
    Cache_Type_ALL
    // All caches
} Cache_Type;
 
 
config Cache_enableCache  // module-wide

Enable L1 data and program caches

C synopsis target-domain
extern const Bool Cache_enableCache;
 
DETAILS
To enable a subset of the caches, set this parameter to 'false' and call Cache_enable() within main, passing it only the Cache_Type(s) to be enabled.
Data caching requires the MMU and the memory section/page descriptor cacheable attribute to be enabled.
 
Cache_disable()  // module-wide

Disables the 'type' cache(s)

C synopsis target-domain
Void Cache_disable(Bits16 type);
 
ARGUMENTS
type — bit mask of Cache type
 
Cache_enable()  // module-wide

Enables all cache(s)

C synopsis target-domain
Void Cache_enable(Bits16 type);
 
ARGUMENTS
type — bit mask of Cache type
 
Cache_inv()  // module-wide

Invalidate the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines in range are invalidated for all the 'type' caches

C synopsis target-domain
Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
 
Cache_invL1dAll()  // module-wide

Invalidate all of L1 data cache

C synopsis target-domain
Void Cache_invL1dAll();
 
DETAILS
This function should be used with caution. In general, the L1 data cache may contain some stack variable or valid data that should not be invalidated. This function should be used only when all contents of L1 data cache is unwanted.
 
Cache_invL1pAll()  // module-wide

Invalidate all of L1 program cache

C synopsis target-domain
Void Cache_invL1pAll();
 
 
Cache_wait()  // module-wide

Wait for a previous cache operation to complete

C synopsis target-domain
Void Cache_wait();
 
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache operation is not truly complete until it has worked its way through all buffering and all memory writes have landed in the source memory.
 
Cache_wb()  // module-wide

Writes back a range of memory from all cache(s)

C synopsis target-domain
Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are left valid in the 'type' caches and the data within the range will be written back to the source memory.
 
Cache_wbAll()  // module-wide

Write back all caches

C synopsis target-domain
Void Cache_wbAll();
 
DETAILS
Perform a global write back. There is no effect on program cache. All data cache lines are left valid.
 
Cache_wbInv()  // module-wide

Writes back and invalidates the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are written back to the source memory and then invalidated for all 'type' caches

C synopsis target-domain
Void Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
 
Cache_wbInvAll()  // module-wide

Write back invalidate all caches

C synopsis target-domain
Void Cache_wbInvAll();
 
DETAILS
Performs a global write back and invalidate. All cache lines are written out to physical memory and then invalidated.
Module-Wide Built-Ins

C synopsis target-domain
Types_ModuleId Cache_Module_id();
// Get this module's unique id
 
Bool Cache_Module_startupDone();
// Test if this module has completed startup
 
IHeap_Handle Cache_Module_heap();
// The heap from which this module allocates memory
 
Bool Cache_Module_hasMask();
// Test whether this module has a diagnostics mask
 
Bits16 Cache_Module_getMask();
// Returns the diagnostics mask for this module
 
Void Cache_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
 
Configuration settings sourced in ti/sysbios/family/arm/arm9/Cache.xdc
var Cache = xdc.useModule('ti.sysbios.family.arm.arm9.Cache');
module-wide constants & types
 
        const Cache.Type_L1D// Level 1 Data cache;
        const Cache.Type_L1// Level 1 caches;
        const Cache.Type_L2D// Level 2 Data cache;
        const Cache.Type_L2// Level 2 caches;
        const Cache.Type_ALLP// All Program caches;
        const Cache.Type_ALLD// All Data caches;
        const Cache.Type_ALL// All caches;
module-wide config parameters
 
 
 
const Cache.sizeL1dCacheLine

Size of L1 data cache Line

Configuration settings
const Cache.sizeL1dCacheLine = 32;
 
C SYNOPSIS
 
const Cache.sizeL1pCacheLine

Size of L1 program cache Line

Configuration settings
const Cache.sizeL1pCacheLine = 32;
 
C SYNOPSIS
 
enum Cache.Type

Lists of bitmask cache types

Configuration settings
values of type Cache.Type
    const Cache.Type_L1P;
    // Level 1 Program cache
    const Cache.Type_L1D;
    // Level 1 Data cache
    const Cache.Type_L1;
    // Level 1 caches
    const Cache.Type_L2P;
    // Level 2 Program cache
    const Cache.Type_L2D;
    // Level 2 Data cache
    const Cache.Type_L2;
    // Level 2 caches
    const Cache.Type_ALLP;
    // All Program caches
    const Cache.Type_ALLD;
    // All Data caches
    const Cache.Type_ALL;
    // All caches
 
C SYNOPSIS
 
config Cache.enableCache  // module-wide

Enable L1 data and program caches

Configuration settings
Cache.enableCache = Bool true;
 
DETAILS
To enable a subset of the caches, set this parameter to 'false' and call Cache_enable() within main, passing it only the Cache_Type(s) to be enabled.
Data caching requires the MMU and the memory section/page descriptor cacheable attribute to be enabled.
C SYNOPSIS
 
metaonly config Cache.common$  // module-wide

Common module configuration parameters

Configuration settings
Cache.common$ = Types.Common$ undefined;
 
DETAILS
All modules have this configuration parameter. Its name contains the '$' character to ensure it does not conflict with configuration parameters declared by the module. This allows new configuration parameters to be added in the future without any chance of breaking existing modules.
generated on Thu, 25 May 2017 22:09:43 GMT