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38
39 package ti.platforms.evmTI811X;
40
41 /*!
42 * ======== Platform ========
43 * Platform support for the evmTI811X
44 *
45 * This module implements xdc.platform.IPlatform and defines configuration
46 * parameters that correspond to this platform's Cpu's, Board's, etc.
47 *
48 * The configuration parameters are initialized in this package's
49 * configuration script (package.cfg) and "bound" to the TCOM object
50 * model. Once they are part of the model, these parameters are
51 * queried by a program's configuration script.
52 *
53 * This particular platform has 4 CPU's, a host GPP, 2 M3's, and a
54 * C674 DSP.
55 */
56 metaonly module Platform inherits xdc.platform.IPlatform
57 {
58 readonly config xdc.platform.IPlatform.Board BOARD = {
59 id: "0",
60 boardName: "evmTI811X",
61 boardFamily: "evmTI811X",
62 boardRevision: null
63 };
64
65
66 readonly config xdc.platform.IExeContext.Cpu GEM = {
67 id: "0",
68 clockRate: 500.0,
69 catalogName: "ti.catalog.c6000",
70 deviceName: "TMS320TI811X",
71 revision: ""
72 };
73
74
75 readonly config xdc.platform.IExeContext.Cpu DSS = {
76 id: "1",
77 clockRate: 200.0,
78 catalogName: "ti.catalog.arm.cortexm3",
79 deviceName: "TMS320TI811X",
80 revision: "1.0"
81 };
82
83
84 readonly config xdc.platform.IExeContext.Cpu GPP = {
85 id: "2",
86 clockRate: 600.0,
87 catalogName: "ti.catalog.arm.cortexa8",
88 deviceName: "TMS320TI811X",
89 revision: "1.0"
90 };
91
92 instance:
93
94 override readonly config xdc.platform.IPlatform.Memory
95 externalMemoryMap[string] = [
96 ["DDR3_HOST", {
97 comment: "DDR3 Memory reserved for use by the A8",
98 name: "DDR3_HOST",
99 base: 0x80000000,
100 len: 0x0B000000
101 }],
102 ["DDR3_DSP", {
103 comment: "DDR3 Memory reserved for use by the C674",
104 name: "DDR3_DSP",
105 base: 0x8B000000,
106 len: 0x02000000
107 }],
108 ["DDR3_SR1", {
109 comment: "DDR3 Memory reserved for use by SharedRegion 1",
110 name: "DDR3_SR1",
111 base: 0x8D000000,
112 len: 0x00C00000
113 }],
114 ["DDR3_HDVPSS", {
115 comment: "DDR3 Memory reserved for use by HDVPSS",
116 name: "DDR3_HDVPSS",
117 base: 0x8DC00000,
118 len: 0x00200000
119 }],
120 ["DDR3_V4L2", {
121 comment: "DDR3 Memory reserved for use by V4L2",
122 name: "DDR3_V4L2",
123 base: 0x8DE00000,
124 len: 0x00200000
125 }],
126 ["DDR3_SR0", {
127 comment: "DDR3 Memory reserved for use by SharedRegion 0",
128 name: "DDR3_SR0",
129 base: 0x8E000000,
130 len: 0x01000000
131 }],
132 ["DDR3_M3", {
133 comment: "DDR3 Memory reserved for use by the M3 core",
134 name: "DDR3_M3",
135 base: 0x8F000000,
136 len: 0x01000000
137 }],
138 ];
139
140 141 142 143 144 145
146 config String l1PMode = "32k";
147
148 149 150 151 152 153
154 config String l1DMode = "32k";
155
156 157 158 159 160 161
162 config String l2Mode = "0k";
163 };