Texas Instruments

Table of Contents

TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432P401R:1

Tool Chain Version: 16.12.0

BIOS Version: bios_6_50_00_06_eng

XDCTools Version: xdctools_3_50_00_09_eng

Benchmark Cycles
Interrupt Latency 135
Hwi_restore() 6
Hwi_disable() 7
Hwi dispatcher prolog 122
Hwi dispatcher epilog 222
Hwi dispatcher 333
Hardware Interrupt to Blocked Task 525
Hardware Interrupt to Software Interrupt 353
Swi_enable() 63
Swi_disable() 9
Post Software Interrupt Again 30
Post Software Interrupt without Context Switch 89
Post Software Interrupt with Context Switch 173
Create a New Task without Context Switch 1647
Set a Task Priority without a Context Switch 141
Task_yield() 206
Post Semaphore No Waiting Task 44
Post Semaphore No Task Switch 165
Post Semaphore with Task Switch 256
Pend on Semaphore No Context Switch 68
Pend on Semaphore with Task Switch 272
Clock_getTicks() 8
POSIX Create a New Task without Context Switch 3224
POSIX Set a Task Priority without a Context Switch 187
POSIX Post Semaphore No Waiting Task 53
POSIX Post Semaphore No Task Switch 176
POSIX Post Semaphore with Task Switch 266
POSIX Pend on Semaphore No Context Switch 81
POSIX Pend on Semaphore with Task Switch 284

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.