Texas Instruments

Table of Contents

IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 7.80.1.28

BIOS Version: bios_6_50_00_06_eng

XDCTools Version: xdctools_3_50_00_09_eng

Benchmark Cycles
Interrupt Latency 119
Hwi_restore() 7
Hwi_disable() 9
Hwi dispatcher prolog 94
Hwi dispatcher epilog 192
Hwi dispatcher 276
Hardware Interrupt to Blocked Task 459
Hardware Interrupt to Software Interrupt 309
Swi_enable() 46
Swi_disable() 11
Post Software Interrupt Again 20
Post Software Interrupt without Context Switch 81
Post Software Interrupt with Context Switch 165
Create a New Task without Context Switch 1385
Set a Task Priority without a Context Switch 138
Task_yield() 180
Post Semaphore No Waiting Task 44
Post Semaphore No Task Switch 170
Post Semaphore with Task Switch 226
Pend on Semaphore No Context Switch 57
Pend on Semaphore with Task Switch 250
Clock_getTicks() 9
POSIX Create a New Task without Context Switch 2652
POSIX Set a Task Priority without a Context Switch 159
POSIX Post Semaphore No Waiting Task 57
POSIX Post Semaphore No Task Switch 182
POSIX Post Semaphore with Task Switch 228
POSIX Pend on Semaphore No Context Switch 49
POSIX Pend on Semaphore with Task Switch 240

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.