Texas Instruments

Table of Contents

IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 7.80.1.28

BIOS Version: bios_6_50_00_06_eng

XDCTools Version: xdctools_3_50_00_09_eng

Benchmark Cycles
Interrupt Latency 151
Hwi_restore() 14
Hwi_disable() 15
Hwi dispatcher prolog 117
Hwi dispatcher epilog 245
Hwi dispatcher 354
Hardware Interrupt to Blocked Task 586
Hardware Interrupt to Software Interrupt 394
Swi_enable() 59
Swi_disable() 16
Post Software Interrupt Again 22
Post Software Interrupt without Context Switch 99
Post Software Interrupt with Context Switch 203
Create a New Task without Context Switch 1843
Set a Task Priority without a Context Switch 185
Task_yield() 228
Post Semaphore No Waiting Task 51
Post Semaphore No Task Switch 216
Post Semaphore with Task Switch 288
Pend on Semaphore No Context Switch 76
Pend on Semaphore with Task Switch 323
Clock_getTicks() 14
POSIX Create a New Task without Context Switch 3587
POSIX Set a Task Priority without a Context Switch 208
POSIX Post Semaphore No Waiting Task 73
POSIX Post Semaphore No Task Switch 234
POSIX Post Semaphore with Task Switch 293
POSIX Pend on Semaphore No Context Switch 67
POSIX Pend on Semaphore with Task Switch 308

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.