Target Platform: ti.platforms.tiva:TM4C123GH6PM:1
Tool Chain Version: 7.80.1.28
BIOS Version: bios_6_50_00_06_eng
XDCTools Version: xdctools_3_50_00_09_eng
Benchmark | Cycles |
---|---|
Interrupt Latency | 143 |
Hwi_restore() | 7 |
Hwi_disable() | 9 |
Hwi dispatcher prolog | 118 |
Hwi dispatcher epilog | 213 |
Hwi dispatcher | 321 |
Hardware Interrupt to Blocked Task | 517 |
Hardware Interrupt to Software Interrupt | 333 |
Swi_enable() | 46 |
Swi_disable() | 11 |
Post Software Interrupt Again | 20 |
Post Software Interrupt without Context Switch | 81 |
Post Software Interrupt with Context Switch | 165 |
Create a New Task without Context Switch | 1417 |
Set a Task Priority without a Context Switch | 138 |
Task_yield() | 214 |
Post Semaphore No Waiting Task | 44 |
Post Semaphore No Task Switch | 170 |
Post Semaphore with Task Switch | 260 |
Pend on Semaphore No Context Switch | 57 |
Pend on Semaphore with Task Switch | 284 |
Clock_getTicks() | 9 |
POSIX Create a New Task without Context Switch | 2684 |
POSIX Set a Task Priority without a Context Switch | 159 |
POSIX Post Semaphore No Waiting Task | 57 |
POSIX Post Semaphore No Task Switch | 182 |
POSIX Post Semaphore with Task Switch | 262 |
POSIX Pend on Semaphore No Context Switch | 49 |
POSIX Pend on Semaphore with Task Switch | 274 |
The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.